Motorola MPC860 PowerQUICC User Manual page 531

The Communications Processor
Intended Audience
Part V is intended for system designers who need to implement various communications
protocols on the MPC860. It assumes a basic understanding of the PowerPC exception
model, the MPC860 interrupt structure, as well as a working knowledge of the
communications protocols to be used. A complete discussion of these protocols is beyond
the scope of this book.
Contents
Part V descibes behavior of the MPC860 communications processor module (CPM) and the
RISC communications processor (CP) that it contains (note that this is separate from the
embedded PowerPC processor).
It contains the following chapters:
¥ Chapter 18, ÒCommunications Processor Module and CPM Timers,Ó provides a
brief overview of the MPC860 CPM and a detailed discussion of the clocking
mechanisms supported.
¥ Chapter 19, ÒCommunications Processor,Ó describes the RISC communications
processor (CP), which handles the low-level communications tasks, freeing the core
for higher-level tasks.
¥ Chapter 20, ÒSDMA Channels and IDMA Emulation,Ó describes the two physical
serial DMA (SDMA) channels on the MPC860 with which the CP implements
sixteen virtual SDMA channels.
¥ Chapter 21, ÒSerial Interface,Ó describes the serial interface (SI) in which the
physical interface to all SCCs and SMCs is implemented.
MOTOROLA Part V. The Communications Processor Module
Part V
Module
V-i