Table of Contents
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Intended Audience
Part IV is intended for system designers who need to understand how each MPC860 signal
works and how those signals interact.
Contents
Part IV descibes external signals, clocking, memory control, and power management of the
MPC860.
It contains the following chapters:
¥ Chapter 13, ÒExternal Signals,Ó provides a detailed description of the external
signals that comprise the MPC860 external interface.
¥ Chapter 14, ÒMPC860 External Bus Interface,Ó describes the interaction between
signals described in the previous chapter, including numerous examples and timing
diagrams.
¥ Chapter 15, ÒClocks and Power Control,Ó describes on-chip and external devices,
including the phase-locked loop circuitry and frequency dividers that generate
programmable clock timing for baud-rate generators, timers, and a variety of low-
power mode options.
¥ Chapter 16, ÒMemory Controller,Ó describes the memory controller, which
controlling a maximum of eight memory banks shared between a general-purpose
chip-select machine (GPCM) and a pair of user-programmable machines (UPMs).
¥ Chapter 17, ÒPCMCIA Interface,Ó describes the PCMCIA host adapter module,
which provides all control logic for a PCMCIA socket interface and requires only
additional external analog power switching logic and buffering.
MOTOROLA
Hardware Interface
Part IV. Hardware Interface
Part IV
IV-i
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