Motorola MPC860 PowerQUICC User Manual page 420

Part IV. Hardware Interface
sequence will be initiated when the power supply to VDDH, VDDL, and VDDSYN is
reapplied.
Some power monitoring circuits drive a reset signal when the power supply voltage falls
below a speciÞed threshold, in order to assure that erratic behavior does not occur in a
low-voltage situation. This functionality can be used with the MPC860,while still
maintaining integrity of the RTC.
The reset signal from the power monitor circuit should be connected to the PORESET
signal of the MPC860. If power dips below the threshold, then PORESET will be driven to
the MPC860, which will reset all of the modules of the MPC860 except the RTC. If power
fails entirely, PORESET will remain asserted, but the RTC will continue to operate if a
backup power supply (e.g. battery) is connected to KAPWR.
In this conÞguration, HRESET and SRESET should be pulled up to VDDH, not to
KAPWR. This is because assertion of PORESET will cause the MPC860 to assert
HRESET and SRESET. If these signals were pulled up to KAPWR, then this would cause
current drain unnecessarily. If HRESET and SRESET are pulled up to VDDH and VDDH
is not powered, then no current drain will result from the HRESET and SRESET assertion.
Note also that PORESET is an input-only signal, and thus does not need a pull-up resistor
if the power monitor circuitÕs reset output is a constantly-driven active driver (i.e. not
three-state).
15.5.7.3 Register Lock Mechanism: Protecting SIU Registers in
Power-Down Mode
If the MPC860 sets PLPRCR[LPM]=11 before entering power-down mode, then the
registers of the SIU maintained by KAPWR are automatically protected. However, to
provide protection of the SIU registers maintained by KAPWR against uncontrolled
shutdown, a register locking mechanism is included. These registers can be write-protected
in a set of associated key registers. For more information on the register lock mechanism,
see Section 11.4.5, ÒRegister Lock Mechanism.Ó
15.5.8 TMIST: Facilitating Nesting of SIU Timer Interrupts
It is often desirable, within an interrupt service routine, to clear the source of the interrupt
at the beginning of the routine, in order to facilitate nesting of interrupts. However, if
normal low mode is enabled, then clearing an interrupt source can cause transition into
normal low mode, which may not be desired. In order to resolve these conßicting interests,
PLPRCR[TMIST] is provided. A timeout in the RTC, PIT, TB, or DEC will cause the
PLPRCR[TMIST] to be set. While PLPRCR[TMIST] is set, entry into low-power mode is
disabled. Thus, the SIU timer interrupt source can be cleared immediately in the interrupt
service routine, while still allowing entry into low-power mode to be enabled at a later,
user-deÞned time (when software clears PLPRCR[TMIST]). Note, however, this requires
that PLPRCR[TMIST] must be cleared before entry into any low-power mode other than
normal high mode.
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