Motorola MPC860 PowerQUICC User Manual page 623

21.2.6.3 GCI Interface (SCIT Mode) Programming Example
Assuming SCC2 is connected to the B1 channel, SMC2 to the B2 channel, SCC3 to the D
channel, and SMC1 to the C/I channels, the initialization sequence is as follows:
1. Program both the Rx and Tx sections of the SI RAM as shown in Table 21-12. Write
all unused entries with 0x0001_0000. Note that this example is for SCIT mode. For
normal mode, delete the last three entries in Table 21-12 and set the LST bit in the
new last entry.
Table 21-12. SI RAM Settings for GCI Interface (SCIT Mode)
Entry
Number
SWTR
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
2. SIMODE = 0x8000_80E0. Only TDMa is used. SMC1 and SMC2 are connected.
3. SICR = 0x00C0_4000. SCC2 and SCC3 are connected to the TSA. SCC3 supports
the grant mechanism since it is on the D channel.
4. PAODR[9] = 1. ConÞgure L1TXDa to be an open-drain output.
5. PAPAR[7Ð9] = 0b111. ConÞgure L1TXDa, L1RXDa, and L1RCLKa.
6. PADIR[7Ð9] = 0b011. ConÞgure L1TXDa, L1RXDa, and L1RCLKa.
7. If the 1´ GCI data clock is required, conÞgure L1CLKOa as an output by setting
PBPAR[20] and PBDIR[20].
8. PCPAR[4] = 1. ConÞgure L1RSYNCa.
9. SIGMR = 0x04. Enable TDMa (one static TDM).
10. SICMR is not used.
11. SISTR and SIRP do not need to be read but can be used for debugging when
channels are enabled.
12. Enable SCC3 for HDLC operation (to handle the LAPD protocol of the D channel),
conÞgure SCC2 and SMC2 as needed and enable SMC1 for SCIT operation.
MOTOROLA
SSEL CSEL CNT
0000 010 0000
0000 110 0000
0000 101 0000
0000 011 0001
0000 101 0101
0000 000 0110
0000 000 0001
0000 111 0000
Chapter 21. Serial Interface
Part V. The Communications Processor Module
SI RAM
BYT LST
1 0
1 0
1 0
0 0
0 0
1 0
0 0
0 1
Description
8 bits SCC2 (B1)
8 bits SMC2 (B2)
8 bits SMC1 (M)
2 bits SCC3 (D)
6 bits SMC1 (I + A + E)
Skip 7 bytes
Skip 2 bits
D grant bit
21-35