Table of Contents
Advertisement
Part II. PowerPC Microprocessor Module
Table 9-16. MI_CAM Field Descriptions (Continued)
Bits
Name
28
SPV
Subpage validity (subpage 0)
0 Subpage 0 (Address[20Ð21] = 00) is not valid
1 Subpage 0 (Address[20Ð21] = 00) is valid
29
0 Subpage 1 (Address[20Ð21] = 01) is not valid
1 Subpage 1 (Address[20Ð21] = 01) is valid
30
0 Subpage 2 (Address[20Ð21] = 10) is not valid
1 Subpage 2 (Address[20Ð21] = 10) is valid
31
0 Subpage 3 (Address[20Ð21] = 11) is not valid
1 Subpage 3 (Address[20Ð21] = 11) is valid
9.8.12.2 IMMU RAM Entry Read Register 0 (MI_RAM0)
The IMMU RAM entry read register 0 (MI_RAM0), shown in Figure 9-18, contains the
physical page number and page attributes of an entry indexed by MI_CTR[ITLB_INDX].
This register is updated only when MI_CAM is updated.
Bit
0
1
Field
Reset
R/W
Bit
16
17
18
Field
RPN
Reset
R/W
SPR
Figure 9-18. IMMU RAM Entry Read Register 0 (MI_RAM0)
Table 9-17 describes MI_RAM0 Þelds.
Bits
Name
0Ð19
RPN
Real (physical) page number
20Ð22 PS_B Page size. (Values not shown are reserved)
000 4 Kbyte
001 16 Kbyte
011 512 Kbyte
111 8 Mbyte
23
CI
Cache-inhibit attribute for the entry
24Ð27 APG
Access protection group. Up to 16 protection groups supported (uses oneÕs complement format)
9-26
2
3
4
5
6
19
20
21
22
PS_B
Table 9-17. MI_RAM0 Field Descriptions
MPC860 PowerQUICC UserÕs Manual
Function
7
8
9
10
11
RPN
Ñ
R
23
24
25
26
27
CI
APG
Ñ
R
817
Description
12
13
14
15
28
29
30
31
SFP
MOTOROLA
Advertisement
Table of Contents
