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Table 16-13. RAM Word Bit Settings (Continued)
Bit
Name
6
BST2 Byte-select timing 2. DeÞnes the state of BS during clock phase 3.
0 Asserted at the rising edge of GCLK2_50.
1 Negated at the rising edge of GCLK2_50
The Þnal value of the BS lines depends on the values of BRx[PS], the TSIZ lines, and A[30Ð31] for
the access. See Section 16.6.4.3, ÒByte-Select Signals (BxTx).Ó
7
BST3 Byte-select timing 3. DeÞnes the state of BS during clock phase 4.
0 Asserted at the falling edge of GCLK1_50.
1 Negated at the falling edge of GCLK1_50.
The Þnal value of the BS lines depends on the values of BRx[PS], the TSIZ lines, and A[30Ð31] for
the access. See Section 16.6.4.3, ÒByte-Select Signals (BxTx).Ó
8Ð9
G0L
General-purpose line 0 lower. DeÞnes the state of GPL0 during phases 1Ð3.
10 Asserted at the falling edge of GCLK2_50.
11 Negated at the falling edge of GCLK2_50.
00 Driven at the falling edge of GCLK2_50 with an address signal as deÞned in MxMR[G0CLx].
10Ð11
G0H
General-purpose line 0 higher. DeÞnes the state of GPL0 during phase 4.
10 Asserted at the falling edge of GCLK1_50.
11 Negated at the falling edge of GCLK1_50.
00 Driven at the falling edge of GCLK1_50 with an address signal as deÞned in MxMR[G0CLx].
12
G1T4 General-purpose line 1 timing 4. DeÞnes the state of GPL1 during phase 1Ð3.
0 Asserted at the falling edge of GCLK2_50.
1 Negated at the falling edge of GCLK2_50.
13
G1T3 General-purpose line 1 timing 3. DeÞnes the state of GPL1 during phase 4.
0 Asserted at the falling edge of GCLK1_50.
1Negated at the falling edge of GCLK1_50.
14
G2T4 General-purpose line 2 timing 4. DeÞnes the state of GPL2 during phase 1Ð3.
0 Asserted at the falling edge of GCLK2_50.
1 Negated at the falling edge of GCLK2_50.
15
G2T3 General-purpose line 2 timing 3. DeÞnes the state of GPL2 during phase 4.
0 Asserted at the falling edge of GCLK1_50.
1 Negated at the falling edge of GCLK1_50.
16
G3T4 General-purpose line 3 timing 4. DeÞnes the state of GPL3 during phase 1Ð3.
0 Asserted at the falling edge of GCLK2_50.
1Negated at the falling edge of GCLK2_50.
17
G3T3 General-purpose line 3 timing 3. DeÞnes the state of GPL3 during phase 4.
0 Asserted at the falling edge of GCLK1_50.
1Negated at the falling edge of GCLK1_50.
18
G4T4/
General-purpose line 4 timing 4/delay time 3. The function is determined by MxMR[GPLx4DIS].
DLT3
G4T4 If MxMR deÞnes UPWAITx/GPL_x4 as an output (GPL_x4), this bit functions as G4T4:
0 The value of GPL4 at the falling edge of GCLK2_50 will be 0.
1 The value of GPL4 at the falling edge of GCLK2_50 will be 1.
DLT3
If MxMR[GPLx4DIS] = 1, UPWAITx is chosen and this bit functions as DLT3.
0 The data bus should be sampled at the rising edge of GCLK2_50 for a read in this cycle.
1 The data bus should be sampled at the falling edge of GCLK2_50 for a read in this cycle.
MOTOROLA
Description
Chapter 16. Memory Controller
Part IV. Hardware Interface
16-37
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