Table of Contents
Advertisement
16.5.1.4 Output Enable (OE) Timing
The timing of the OE is affected only by TRLX. It always asserts and negates on the rising
or falling edge of the external bus clock. OE always asserts on the rising clock edge after
CS is asserted, and therefore its assertion can be delayed (along with the assertion of CS)
by programming TRLX = 1. OE deasserts on the rising clock edge coinciding with or
immediately following CS deassertion.
16.5.1.5 Programmable Wait State ConÞguration
The GPCM supports internal TA generation. It allows fast accesses to external memory
through an internal bus master or a maximum 17-clock access by programming ORx[SCY].
The internal TA generation mode is enabled if ORx[SETA] is cleared. If TA is asserted
externally at least two clock cycles before the wait state counter has expired, the current
memory cycle is terminated. When TRLX is set, the number of wait states inserted by the
memory controller is deÞned by 2 x SCY or a maximum of 30 wait states.
16.5.1.6 Extended Hold Time on Read Accesses
Slow memory devices that take a long time to turn off their data bus drivers on read accesses
should set ORx[EHTR]. Any GPCM access to the external bus following a read access to
the slower memory bank is delayed by one clock cycle, unless it is a read access to the same
bank. See Figure 16-25 through Figure 16-28 for details.
Clock
Address
TS
TA
CSx
CSy
R/W
OE
Data
Figure 16-25. GPCM Read Followed by Write (EHTR = 0)
MOTOROLA
Hold Time
Chapter 16. Memory Controller
Part IV. Hardware Interface
16-25
Advertisement
Table of Contents
