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Part II. PowerPC Microprocessor Module
9.8.7 DMMU Real Page Number Register (MD_RPN)
The DMMU real page number register (MD_RPN), shown in Figure 9-12, contains the
physical address and the memory attributes of an entry to be loaded into a TLB. This
register should be written after the MD_EPN and MD_TWC registers.
Bit
0
1
Field
Reset
R/W
Bit
16
17
Field
RPN
Reset
R/W
SPR
Figure 9-12. DMMU Real Page Number Register (MD_RPN)
Table 9-12 describes MD_RPN Þelds.
4-Kbyte Pages AND
Bits
Name
(MD_CTR[PPM] = 1)
0Ð19
RPN
Real (physical) page number
20Ð21 PP
Protection attributes for
subpages 1Ð4 in a 4-Kbyte
page.
Supervisor User
00 No access No access
01 R/W
10 R/W
22
11 R/W
23
24Ð25
26Ð27
28
SPS
Small page size: Clear.
9-22
2
3
4
5
18
19
20
21
22
Table 9-12. MD_RPN Field Descriptions
Extended Encoding:
Supervisor
00 No access
01 R/O
1x Reserved
No access
R/O
0 Bits 20Ð21 contain PowerPC encoding
R/W
1 Bits 20Ð21 contain extended encoding
Change bit for DTLB entry. Set to 1 by default if change tracking
functionality is not desired.
0 Unchanged region. Write access causes an IMMU exception.
Software should take an appropriate action before setting this bit.
1 Changed region. Write access is allowed to this page.
MD_CTR[PPCS] = 0
For 1 Kbyte pages in mode 3, set to
the appropriate subpage validity
(see Section 9.5, ÒProtection
Resolution ModesÓ). Otherwise, set
to 0b1111.
Small page size. Valid only when L1 descriptor[PS] = 00
0 4 Kbyte
1 16 Kbyte
MPC860 PowerQUICC UserÕs Manual
6
7
8
9
10
RPN
Ñ
R/W
23
24
25
26
PP
Ñ
R/W
798
Greater than 4-Kbyte Pages OR MD_CTR[PPM] = 0
User
No access
No access
11
12
13
14
27
28
29
30
SPS
SH
CI
PowerPC Encoding:
Supervisor
User
00 R/W
No access
01 R/W
R/O
10 R/W
R/W
11 R/O
R/O
MD_CTR[PPCS] = 1
1000 Hit only for supervisor
accesses
0100 Hit only for user accesses
1100 Hit for both
MOTOROLA
15
31
V
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