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reads the transfer-speciÞc information from the current BD into the IDMA parameter
RAM, programs the physical SDMA channel, and provides addressing and bus control. The
termination phase begins when the transfer byte count reaches zero (or a bus error occurs).
The CPM then interrupts the core (unless masked), and the current BD pointer moves to the
next BD in the table.
To begin a block transfer, initialize the IDMA registers, and build the IDMA BDs with
information describing the data block, device type, and other special control options. See
Section 20.3.2, ÒIDMA Parameter RAM,Ó and Section 20.3.5, ÒIDMA CP Commands.Ó
20.3.6.1 Activating an IDMA Channel
IDMA requests are generated externally via the DREQ signals. (There is no mechanism for
generating internal IDMA requests.) After initializing the IDMA parameter RAM and the
BD table, enable the DREQ signal by setting the corresponding PCSO[DREQ] of the
port C special options register; see Section 34.4.1.4, ÒPort C Special Options Register
(PCSO).Ó Enabling the DREQ signal effectively activates the corresponding IDMA
channel. Requests for IDMA1 have priority over IDMA2.
20.3.6.2 Suspending an IDMA Channel
Disabling the corresponding DREQ signal by clearing the corresponding PCSO[DREQ]
suspends the IDMA channel transfer. A transfer in progress will be completed before the
bus is released. No further bus cycles are started while PCSO[DREQ] remains cleared.
During channel suspension, the core can access IDMA internal registers to determine the
status of the channel or to alter parameters. If PCSO[DREQ] is set again while a transfer
request is pending, the channel arbitrates for the bus and continues normal operation.
20.3.7 IDMA Interface SignalsÑDREQ and SDACK
Each IDMA channel (IDMA1 and IDMA2) has two dedicated control signalsÑDMA
request (DREQ) and SDMA acknowledge (SDACK). DREQ0 and SDACK1 are dedicated
to IDMA1, while DREQ1 and SDACK2 are for IDMA2. DREQ and SDACK are the
handshake signals between the MPC860 and an external device requesting service. A
peripheral requests IDMA service directly to the CPM by asserting DREQ. When the CPM
begins the transfer, it acknowledges the device by asserting SDACK. A requesting device
can either be the source or the destination of an IDMA transfer.
20.3.7.1 IDMA Requests for Memory/Memory Transfers
Because there is no internal mechanism, an externally-connected DREQ must still be used
to generate IDMA memory/memory transfer requests. This can be done using a
general-purpose I/O line or a general-purpose timer output.
To use a general-purpose I/O line, follow these steps:
1. Externally connect a general-purpose output line to DREQ.
2. Set RCCR[DRnM] (level-sensitive).
3. Drive the output low when the request generation should begin.
MOTOROLA
Chapter 20. SDMA Channels and IDMA Emulation
Part V. The Communications Processor Module
20-13
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