Motorola MPC860 PowerQUICC User Manual page 964

Part VI. Debug and Test
Event Name
G (Gmatch0 | Gmatch1 | Gmatch2 | Gmatch3)
H (Hmatch0 | Hmatch1 | Hmatch2 | Hmatch3)
1
(G & H) ((Gmatch0 & Hmatch0) | (Gmatch1 & Hmatch1) | (Gmatch2 & Hmatch2) | (Gmatch3 & Hmatch3))
1
(G | H) ((Gmatch0 | Hmatch0) | (Gmatch1 | Hmatch1) | (Gmatch2 | Hmatch2) | (Gmatch3 | Hmatch3))
1
& denotes a logical AND. | denotes a logical OR.
The four load/store data events, combined with the match events of the load/store address
comparators and the instruction watchpoints, are used to generate the load/store
watchpoints and breakpoint according to the userÕs programming.
Table 37-8. Load/Store Watchpoints Programming Options
Name Description
LW0 First load/store
watchpoint
LW1 Second
load/store
watchpoint
When programming load/store watchpoints to ignore L-addr events and L-data events, the
instruction must be a load/store instruction for the load/store watchpoint event to trigger.
37.2.3.3 The Counters
Each of the two 16-bit down counters can count an instruction watchpoint or a load/store
watchpoint. Both generate the corresponding breakpoint when they reach zero. In masked
mode, counters do not count detected watchpoints when MSR[RI] = 0. See
Section 37.2.4.3, ÒContext Dependent Filter.Ó Counter values are not predictable if they
count watchpoints programmed on instructions that alter counters directly. Readings from
the counters when active must be synchronized by inserting a sync instruction before the
read.
Note that when programmed to count instruction watchpoints, the last instruction that
decrements the counter to zero is treated like any other instruction breakpoint in that it is
not executed before the machine branches to the breakpoint exception routine. As a side
effect of this behavior, the value of the counter inside the breakpoint exception routine
equals one and not zero, as one might expect. When programmed to count load/store
watchpoints, the last instruction that decrements the counter to zero is treated like any other
37-14
Table 37-7. Load/Store Data Events
Event Function (see note)
Instruction Events
Programming Options
IW0, IW1, IW2, IW3,
ignore instruction
events
IW0, IW1, IW2, IW3,
ignore instruction
events
MPC860 PowerQUICC UserÕs Manual
L-Address Events
Programming Options
Comparator E
Comparator F
Comparators (E & F)
Comparators (E | F)
Ignore L-address events
Comparator E
Comparator F
Comparators (E & F)
Comparators (E | F)
Ignore I-address events
L-Data Events
Programming Options
Comparator G
Comparator H
Comparators (G & H)
Comparators (G | H)
Ignore L-data events
Comparator G
Comparator H
Comparators (G & H)
Comparators (G | H)
Ignore L-data events
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