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overview, 35-1
registers, 35-6
source priorities, 35-3
DSP function, 36-6
Communication processor module (CPM)
parallel interface port
block diagram, 33-2
buffer descriptors, 33-11
BUSY signal (Centronics interface), 33-17
Centronics interface, implementation, 33-19
Centronics receive errors, 33-22
Centronics receiver, 33-22
Centronics transmit errors, 33-21
Centronics transmitter, 33-20
control character table, 33-6
CP commands, 33-14
features, 33-1
handshaking I/O modes, 33-15
interlocked handshake mode, 33-15
overview, 33-1
parameter RAM, 33-3
pulsed handshake mode, 33-16
RCCM/RCCR, 33-6
registers, 33-4, 33-7
transparent transfers, 33-19
Communications processor
communicating with peripherals, 19-2
communicating with the core, 19-2
CP command execution latency, 19-9
dual-port RAM, 19-9
features summary, 19-1
host command opcodes, 19-7
overview, 19-1
parameter RAM, 19-11
PWM mode, 19-15
RISC timer initialization, 19-16
RISC timer tables, 19-12
SET TIMER command, 19-13
tracking CP loading, 19-17
Communications processor module (CPM)
asynchronous HDLC mode, 26-1
average rate limitation, B-2
communications processor
overview, 19-1
CPM bandwidth, B-2
DSP function execution times, 36-33
DSP performance (core vs. CPM), 36-30
features list, 18-1
IrDA, 26-1
performance calculation, 36-33
performance calculations, B-5
SCC BISYNC mode, 27-1
SCC Ethernet mode, 28-1
SCC Transparent mode, 29-1
MOTOROLA
INDEX
serial interface
overview, 21-1
timers, 18-4
Comparator value (CMPAÐCMPH) registers, 37-37
Compare instructions, D-18
Completion queue timing, full, 10-4
compliant with the Book 1 specification for the
PowerPC architecture. The PowerPC core is a
fully static design that consist, 1-6
Context synchronization, 6-6
Conventions
notational conventions, lxix, ix, xiv, xxx, xxxvi
terminology, lxxiii, xxi
copyback buffer, 8-15
CPCR (CP command register), 19-6
CPM interrupt configuration (CICR) register, 35-7
CPM interrupt controller
overview, 35-1
CPM interrupt controller (CPIC)
calculating interrupt vectors, 35-5
features, 35-1
generating interrupt vectors, 35-5
highest priority interrupt, 35-4
interrupt handler examples, 35-10
masking interrupt sources, 35-4
nested interrupts, 35-4
registers, 35-6
source priorities, 35-3
CPM interrupt in-service register (CISR), 35-9
CPM interrupt mask (CIMR) register, 35-9
CPM interrupt pending (CIPR) register, 35-8
CPM interrupt vector register (CIVR), 35-10
CPM see Communications processor module (CPM)
CR (cancel reservation) signal, 3-5, 13-6, 14-4
CR (condition register), 5-2
CSn (chip select) signals, 3-6, 13-8
D
Data bus
contents for write cycles, 14-25
requirements for read cycles, 14-25
Data cache miss timing, 10-3
DC_ADR (data cache address) register, 8-13
DC_CST (data cache control and status) register, 8-12
DC_CST commands, 8-15
DC_DAT (data cache data port) register, 8-14
DCMR (DMA channel mode register), 20-7
DCMR (IDMA1 channel mode register, single-buffer
mode), 20-19
Debug enable register (DER), 37-46
Debug mode, 37-32
Debug mode operation, 37-21
Debug port hard/soft reset, 12-3
Debug support, 8-29, 37-1
Index
Index--3
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