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Communications Processor Module and CPM Timers
SDMA Channels and IDMA Emulation
SCC Asynchronous HDLC Mode and IrDA
System Development and Debugging
Serial Communciation Performance
MPC860 Overview
Memory Map
Hardware Interface Overview
PowerPC Core Overview
PowerPC Core Register Set
MPC860 Instruction Set
PowerPC Exceptions
Instruction and Data Caches
Memory Management Unit
Instruction Execution Timing
System Interface Unit
External Signals
MPC860 External Bus Interface
Clocks and Power Control
Memory Controller
PCMCIA Interface
Communications Processor
Serial Interface
SCC Introduction
SCC UART Mode
SCC HDLC Mode
SCC AppleTalk Mode
SCC BISYNC Mode
SCC Ethernet Mode
SCC Transparent Mode
Serial Management Controller
Serial Peripheral Interface
2
I C Controller
Parallel Interface Port
Parallel I/O Port
CPM Interrupt Controller
Digital Signal Processing
IEEE 1149.1 Test Access Port
Byte Ordering
Register Quick Reference Guide
MPC860 Instruction Set
1
2
3
4
5
6
7
8
9
10
11
12
Reset
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A
B
C
D
Glossary
GLO
Index
IND

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   Related Manuals for Motorola MPC860 PowerQUICC

   Summary of Contents for Motorola MPC860 PowerQUICC

  • Page 1

    MPC860 Overview Memory Map Hardware Interface Overview PowerPC Core Overview PowerPC Core Register Set MPC860 Instruction Set PowerPC Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing System Interface Unit Reset External Signals MPC860 External Bus Interface Clocks and Power Control Memory Controller PCMCIA Interface Communications Processor Module and CPM Timers...

  • Page 2

    MPC860 Overview Memory Map Hardware Interface Overview PowerPC Core Overview PowerPC Core Register Set MPC860 Instruction Set PowerPC Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing System Interface Unit Reset External Signals MPC860 External Bus Interface Clocks and Power Control Memory Controller PCMCIA Interface Communications Processor Module and CPM Timers...

  • Page 3

    MPC860UM/AD 07/98 REV. 1 ª MPC860 PowerQUICC UserÕs Manual...

  • Page 4

    Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and speciÞcally disclaims any and all liability, including without limitation consequential or incidental damages.

  • Page 5

    Embedded PowerPC Core..................1-6 System Interface Unit (SIU).................1-7 PCMCIA Controller .....................1-7 Power Management....................1-7 Communications Processor Module (CPM) ............1-8 Software Compatibility Issues ................1-9 Chapter 2 Memory Map Chapter 3 Hardware Interface Overview System Bus Signals ....................3-3 System Bus Signals ....................3-3 MOTOROLA Contents...

  • Page 6

    PowerPC RegistersÑSupervisor Registers............5-4 5.1.2.1 DAR, DSISR, and BAR Operation ..............5-5 5.1.2.2 Unsupported Registers .................5-6 5.1.2.3 PowerPC Supervisor-Level Register Bit Assignments ........5-6 5.1.2.3.1 Machine State Register (MSR) ..............5-6 5.1.2.3.2 Processor Version Register ..............5-8 5.1.3 MPC860-Specific SPRs..................5-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 7

    Integer Load and Store String Instructions ..........6-14 6.2.4.3 Branch and Flow Control Instructions ............6-15 6.2.4.3.1 Branch Instruction Address Calculation ..........6-15 6.2.4.3.2 Branch Instructions ................6-16 6.2.4.3.3 Condition Register Logical Instructions ..........6-16 6.2.4.4 Trap Instructions ..................6-17 6.2.4.5 Processor Control Instructions ..............6-17 MOTOROLA Contents...

  • Page 8

    Implementation-Specific Exceptions..............7-12 7.1.3.1 Software Emulation Exception (0x01000) ..........7-12 7.1.3.2 Instruction TLB Miss Exception (0x01100) ..........7-12 7.1.3.3 Data TLB Miss Exception (0x01200) ............7-13 7.1.3.4 Instruction TLB Error Exception (0x01300)..........7-13 7.1.3.5 Data TLB Error Exception (0x014000)............7-14 viii MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 9

    Data Cache Block Flush (dcbf)..............8-20 8.4.6 Data Cache Block Invalidate (dcbi)...............8-20 Instruction Cache Operations ................8-20 8.5.1 Instruction Cache Hit ..................8-22 8.5.2 Instruction Cache Miss...................8-22 8.5.3 Instruction Fetching on a Predicted Path ............8-23 8.5.4 Fetching Instructions from Caching-Inhibited Regions.........8-23 MOTOROLA Contents...

  • Page 10

    DMMU Tablewalk Control Register (MD_TWC).........9-19 9.8.6 IMMU Real Page Number Register (MI_RPN)..........9-20 9.8.7 DMMU Real Page Number Register (MD_RPN)..........9-22 9.8.8 MMU Tablewalk Base Register (M_TWB) ...........9-23 9.8.9 MMU Current Address Space ID Register (M_CASID) .......9-23 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 11

    Accessing Off-Core SPRs ................10-8 Chapter 11 System Interface Unit 11.1 Features ......................11-1 11.2 System Configuration and Protection ..............11-2 11.3 Multiplexing SIU Pins..................11-3 11.4 Programming the SIU..................11-4 11.4.1 Internal Memory Map Register (IMMR) ............11-4 11.4.2 SIU Module Configuration Register (SIUMCR) ...........11-5 MOTOROLA Contents...

  • Page 12

    PIT Register (PITR) ..................11-33 11.12 General SIU Timers Operation.................11-33 11.12.1 Freeze Operation ..................11-33 11.12.2 Low-Power Stop Operation................11-34 Chapter 12 Reset 12.1 Types of Reset ....................12-1 12.1.1 Power-On Reset....................12-2 12.1.2 External Hard Reset..................12-2 12.1.3 Internal Hard Reset..................12-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 13

    Bus Transfer Overview ..................14-1 14.3 Bus Interface Signal Descriptions ..............14-2 14.4 Bus Operations ....................14-6 14.4.1 Basic Transfer Protocol..................14-6 14.4.2 Single-Beat Transfer ..................14-7 14.4.2.1 Single-Beat Read Flow ................14-7 14.4.2.2 Single-Beat Write Flow ................14-9 14.4.3 Burst Transfers .....................14-13 14.4.4 Burst Operations...................14-14 MOTOROLA Contents xiii...

  • Page 14

    SPLL Reset Configuration .................15-6 15.2.2.2 SPLL Output Characteristics and Stability ..........15-7 15.2.2.3 The System Phase-Locked Loop Pins (VDDSYN, VSSSYN, VSSSYN1, XFC) ...................15-8 15.2.2.4 Disabling the SPLL ..................15-9 15.3 Clock Signals......................15-9 15.3.1 Clocks Derived from the SPLL Output ............15-9 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 15

    16.1 Features ......................16-1 16.2 Basic Architecture ....................16-4 16.3 Chip-Select Programming Common to the GPCM and UPM ......16-6 16.3.1 Address Space Programming .................16-7 16.3.2 Register Programming Order .................16-7 16.3.3 Memory Bank Write Protection ..............16-7 16.3.4 Address Type Protection ................16-7 MOTOROLA Contents...

  • Page 16

    General-Purpose Signals (GxTx, GOx)............16-40 16.6.4.5 Loop Control (LOOP) ................16-42 16.6.4.6 Exception Pattern Entry (EXEN) .............16-43 16.6.4.7 Address Multiplexing (AMX) ..............16-43 16.6.4.8 Transfer Acknowledge and Data Sample Control (UTA, DLT3) ....16-47 16.6.4.9 Disable Timer Mechanism (TODT) ............16-48 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 17

    Power Control ....................17-7 17.3.5 Reset and Three-State Control ...............17-7 17.3.6 DMA ......................17-7 17.4 Programming Model ..................17-8 17.4.1 PCMCIA Interface Input Pins Register (PIPR) ..........17-8 17.4.2 PCMCIA Interface Status Changed Register (PSCR) ........17-9 17.4.3 PCMCIA Interface Enable Register (PER)..........17-10 MOTOROLA Contents xvii...

  • Page 18

    CP Command Register (CPCR) ..............19-6 19.5.3 CP Commands ....................19-7 19.5.3.1 CP Command Examples................19-8 19.5.3.2 CP Command Execution Latency ..............19-9 19.6 Dual-Port RAM ....................19-9 19.6.1 System RAM and Microcode Packages ............19-10 19.6.2 The Buffer Descriptor (BD) .................19-11 xviii MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 19

    IDMA Channel Operation................20-12 20.3.6.1 Activating an IDMA Channel ..............20-13 20.3.6.2 Suspending an IDMA Channel ..............20-13 20.3.7 IDMA Interface SignalsÑDREQ and SDACK...........20-13 20.3.7.1 IDMA Requests for Memory/Memory Transfers ........20-13 20.3.7.2 IDMA Requests for Peripheral/Memory Transfers .........20-14 20.3.7.2.1 Level-Sensitive Requests ..............20-14 MOTOROLA Contents...

  • Page 20

    SI RAM Pointer Register (SIRP) .............21-26 21.2.5 IDL Bus Implementation................21-28 21.2.5.1 ISDN Terminal Adaptor Application ............21-28 21.2.5.2 Programming the IDL Interface ...............21-31 21.2.6 GCI Bus Implementation................21-32 21.2.6.1 GCI Activation/Deactivation..............21-34 21.2.6.2 Programming the GCI Interface ...............21-34 21.2.6.2.1 Normal Mode ..................21-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 21

    22.3.7.4 Reset Sequence for an SCC Receiver ............22-27 22.3.7.5 Switching Protocols .................22-27 22.3.8 Saving Power ....................22-27 Chapter 23 SCC UART Mode 23.1 Features ......................23-2 23.2 Normal Asynchronous Mode ................23-3 23.3 Synchronous Mode.....................23-3 23.4 SCC UART Parameter RAM ................23-4 MOTOROLA Contents...

  • Page 22

    24.13.2 SCC HDLC Programming Example #2 ............24-16 24.14 HDLC Bus Mode with Collision Detection .............24-16 24.14.1 HDLC Bus Features ..................24-19 24.14.2 Accessing the HDLC Bus................24-19 24.14.3 Increasing Performance ................24-20 24.14.4 Delayed RTS Mode ..................24-21 xxii MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 23

    Asynchronous HDLC Event Register (SCCE)/Asynchronous HDLC Mask Register (SCCM)................26-9 26.13.2 SCC Asynchronous HDLC Status Register (SCCS)........26-10 26.13.3 Asynchronous HDLC Mode Register (PSMR)..........26-11 26.14 SCC Asynchronous HDLC RxBDs..............26-11 26.15 SCC Asynchronous HDLC TxBDs..............26-13 26.16 Differences between HDLC and Asynchronous HDLC ........26-14 MOTOROLA Contents xxiii...

  • Page 24

    Parallel CAM Interface.................28-10 28.8 SCC Ethernet Parameter RAM.................28-12 28.9 Programming the Ethernet Controller ..............28-14 28.10 SCC Ethernet Commands.................28-14 28.11 SCC Ethernet Address Recognition ..............28-16 28.12 Hash Table Algorithm ..................28-17 28.13 Interpacket Gap Time ..................28-18 xxiv MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 25

    29.10 SCC Transparent Receive Buffer Descriptor (RxBD) ........29-9 29.11 SCC Transparent Transmit Buffer Descriptor (TxBD)........29-10 29.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)....29-12 29.13 SCC Status Register in Transparent Mode (SCCS) .........29-13 29.14 SCC2 Transparent Programming Example ............29-13 MOTOROLA Contents...

  • Page 26

    SMC Transparent Commands ..............30-25 30.4.8 Handling Errors in the SMC Transparent Controller ........30-26 30.4.9 SMC Transparent Receive BD (RxBD) ............30-26 30.4.10 SMC Transparent Transmit BD (TxBD)............30-27 30.4.11 SMC Transparent Event Register (SMCE)/Mask Register (SMCM) ..30-29 xxvi MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 27

    The SPI Buffer Descriptor (BD) Table ............31-13 31.7.1 SPI Buffer Descriptors (BDs) ..............31-14 31.7.1.1 SPI Receive BD (RxBD)................31-14 31.7.1.2 SPI Transmit BD (TxBD) ................31-15 31.8 SPI Master Programming Example..............31-17 31.9 SPI Slave Programming Example ..............31-18 31.10 Handling Interrupts in the SPI................31-19 MOTOROLA Contents xxvii...

  • Page 28

    Control Character Table, RCCM, and RCCR ..........33-6 33.4 The PIP Registers ....................33-7 33.4.1 PIP Configuration Register (PIPC) ..............33-7 33.4.2 PIP Event Register (PIPE)................33-9 33.4.3 PIP Mask Register ..................33-10 33.4.4 PIP Timing Parameters Register (PTPR) .............33-10 33.4.5 The Port B Registers..................33-10 xxviii MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 29

    34.4.1.1 Port C Data Register (PCDAT)..............34-15 34.4.1.2 Port C Data Direction Register (PCDIR) ..........34-15 34.4.1.3 Port C Pin Assignment Register (PCPAR) ..........34-15 34.4.1.4 Port C Special Options Register (PCSO) ..........34-16 34.4.1.5 Port C Interrupt Control Register (PCINT)..........34-17 MOTOROLA Contents xxix...

  • Page 30

    DSP Function Priority within the CPM..............36-6 36.10 DSP Event/Mask Registers (SDSR/SDMR)............36-7 36.11 FIR Library Functions ..................36-7 36.11.1 FIR1ÐReal C, Real X, and Real Y..............36-8 36.11.1.1 FIR1 Coefficient, Input, and Output Buffers ..........36-8 36.11.1.2 FIR1 Function Descriptor................36-9 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 31

    LMS2 Applications ..................36-28 36.17 Weighted Vector Addition (WADD)ÐReal X and Real Y.......36-28 36.17.1 WADD Coefficients and Input Buffers............36-28 36.17.2 WADD Function Descriptor ................36-29 36.17.3 WADD Applications..................36-30 36.18 DSP Performance Using the Core Alone Versus Using the CPM ....36-30 MOTOROLA Contents xxxi...

  • Page 32

    37.2.4.4 Ignore First Match ..................37-17 37.2.4.5 Generating Six Compare Types ...............37-18 37.2.5 Load/Store Breakpoint Example ..............37-18 37.3 Development System Interface.................37-19 37.3.1 Debug Mode Operation ................37-21 37.3.1.1 Debug Mode Enable vs. Debug Mode Disable ........37-22 xxxii MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 33

    Load/Store Support AND-OR Control Register (LCTRL2)....37-41 37.5.1.6 Breakpoint Counter Value and Control Registers (COUNTA/COUNTB).................37-43 37.5.2 Debug Mode Registers.................37-44 37.5.2.1 Interrupt Cause Register (ICR) ..............37-44 37.5.2.2 Debug Enable Register (DER) ..............37-46 37.5.2.3 Development Port Data Register (DPDR) ..........37-47 MOTOROLA Contents xxxiii...

  • Page 34

    CLAMP ......................38-7 38.4.5 HIÐZ .......................38-7 38.5 TAP Usage Considerations.................38-7 38.6 Recommended TAP Configuration ..............38-8 38.7 Motorola MPC860 BSDL Description ...............38-8 Appendix A Byte Ordering Byte Ordering Overview ..................A-1 MPC860 Byte-Ordering Mechanisms ..............A-1 BE Mode......................A-2 TLE Mode......................A-2 A.4.1 TLE Mode System Examples................A-4 PPC-LE Mode......................A-6...

  • Page 35

    MPC860-Specific SPRs ..................C-2 Appendix D MPC860 Instruction Set Listings Instructions Sorted by Mnemonic ............... D-1 Instructions Sorted by Opcode ................D-9 Instructions Grouped by Functional Categories..........D-17 Instructions Sorted by Form................D-27 Instruction Set Legend ..................D-38 MOTOROLA Contents xxxv...

  • Page 36

    CONTENTS Paragraph Page Title Number Number xxxvi MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 37

    IMMU Real Page Number Register (MI_RPN) ..........9-21 9-12 DMMU Real Page Number Register (MD_RPN) ..........9-22 9-13 MMU Tablewalk Base Register (M_TWB) ............9-23 9-14 MMU Current Address Space ID Register (M_CASID)........9-23 9-15 MMU Access Protection Registers (MI_AP/MD_AP)........9-24 MOTOROLA Illustrations xxxvii...

  • Page 38

    11-21 Timebase Reference Registers (TBREFA and TBREFB) ....... 11-25 11-22 Timebase Status and Control Register (TBSCR)..........11-26 11-23 Real-Time Clock Block Diagram ..............11-27 11-24 Real-Time Clock Status and Control Register (RTCSC) ........ 11-27 xxxviii MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 39

    Internal Operand Representation ..............14-24 14-20 Interface to Different Port Size Devices ............14-24 14-21 Bus Arbitration Flowchart ................14-26 14-22 Masters Signals Basic Connection..............14-27 14-23 Bus Arbitration Timing Diagram..............14-28 14-24 Internal Bus Arbitration State Machine ............14-29 MOTOROLA Illustrations xxxix...

  • Page 40

    Memory Periodic Timer Prescaler Register (MPTPR)........16-17 16-15 GPCM-to-SRAM Configuration..............16-18 16-16 GPCM Peripheral Device Interface ..............16-20 16-17 GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0)....16-20 16-18 GPCM Memory Device Interface..............16-21 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 41

    Synchronous External Master Interconnect Example........16-55 16-50 Synchronous External Master: Burst Read Access to Page Mode DRAM ..16-56 16-51 Asynchronous External Master Interconnect Example........16-57 16-52 Asynchronous External Master Timing Example..........16-58 16-53 Page-Mode DRAM Interface Connection ............16-59 MOTOROLA Illustrations...

  • Page 42

    CPM Block Diagram..................18-2 18-2 MPC860 Application Design Example.............. 18-4 18-3 CPM Timer Block Diagram................18-5 18-4 Timer Cascaded Mode Block Diagram.............. 18-7 18-5 Timer Global Configuration Register (TGCR)..........18-8 18-6 Timer Mode Registers (TMR1ÐTMR4)............. 18-9 xlii MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 43

    SI RAM Partitioning Using Two TDMs with Dynamic Frames ..... 21-13 21-10 SIRAM Entry ....................21-14 21-11 Example Using SI RAMn[SWTR] ..............21-15 21-12 SI Global Mode Register (SIGMR) ..............21-17 21-13 SI Mode Register (SIMODE) ................21-18 MOTOROLA Illustrations xliii...

  • Page 44

    SCC UART Receiving using RxBDs .............. 23-16 23-8 SCC UART RxBD................... 23-17 23-9 SCC UART Transmit Buffer Descriptor (TxBD)..........23-18 23-10 SCC UART Interrupt Event Example.............. 23-20 23-11 SCC UART Event Register (SCCE) and Mask Register (SCCM) ....23-20 xliv MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 45

    BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)....27-15 27-9 SCC Status Registers (SCCS)................27-16 28-1 Ethernet Frame Structure ................... 28-1 28-2 Ethernet Block Diagram ..................28-2 28-3 Connecting the MPC860 to Ethernet ..............28-6 28-4 MPC860 Ethernet Serial CAM Interface............28-10 MOTOROLA Illustrations...

  • Page 46

    SPI Transfer Format with SPMODE[CP] = 1 ........... 31-8 31-7 SPI Event/Mask Registers (SPIE/SPIM) ............31-10 31-8 SPI Command Register (SPCOM)..............31-10 31-9 Receive/Transmit Function Code Registers (RFCR/TFCR)......31-12 31-10 SPI Memory Structure ..................31-13 xlvi MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 47

    34-2 Port A Data Register (PADAT) ................. 34-4 34-3 Port A Data Direction Register (PADIR) ............34-5 34-4 Port A Pin Assignment Register (PAPAR)............34-5 34-5 Block Diagram for PA15 (True for all Non-Open-Drain Port Signals)..... 34-7 MOTOROLA Illustrations xlvii...

  • Page 48

    FIR5 Fractionally Spaced Equalizer Example..........36-17 36-21 FIR6 Function Descriptor ................36-18 36-22 IIR Function ..................... 36-19 36-23 IIR Function Descriptor ................... 36-20 36-24 MOD Function ....................36-21 36-25 MOD Function Descriptor ................36-22 xlviii MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 49

    Observe-Only Input Signal Boundary Scan Cell (Input Cell) ......38-4 38-5 Input/Output Control Boundary Scan Cell (I/O Control Cell)......38-5 38-6 Bidirectional (I/O) Signal Boundary Scan Cell ..........38-5 38-7 Bypass Register....................38-7 TLE Mode Mechanisms..................A-3 MOTOROLA Illustrations xlix...

  • Page 50

    ILLUSTRATIONS Figure Page Title Number Number Byte Swapping ....................A-4 PPC-LE Mode Mechanisms................A-7 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 51

    Integer Load and Store with Byte-Reverse Instructions........6-14 6-10 Integer Load and Store Multiple Instructions............6-14 6-11 Integer Load and Store String Instructions............6-14 6-12 Branch Instructions....................6-16 6-13 Condition Register Logical Instructions..............6-16 6-14 Trap Instructions....................6-17 6-15 Move to/from Condition Register Instructions............6-17 MOTOROLA Contents...

  • Page 52

    DC_DAT Format when Reading a Tag..............8-15 8-11 Copyback Buffer Select Field (DC_CST[21Ð27]) Encoding ........ 8-15 Identical Entries Required in Level-One/Level-Two Tables ........ 9-11 Number of Replaced EA Bits per Page Size ............9-13 Level-One Segment Descriptor Format..............9-13 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 53

    TBU Field Descriptions..................11-25 11-17 TBL Field Descriptions ..................11-25 11-18 TBREFA/TBREFB Field Descriptions ............... 11-26 11-19 TBSCR Field Descriptions .................. 11-26 11-20 RTCSC Field Descriptions .................. 11-28 11-21 RTC Field Description ..................11-28 11-22 RTCAL Field Descriptions.................. 11-29 MOTOROLA Contents liii...

  • Page 54

    Boot Bank Field Values after Reset ..............16-28 16-13 RAM Word Bit Settings ..................16-36 16-14 Enabling Byte-Selects ..................16-40 16-15 GPL_X5 Signal Behavior..................16-41 16-16 MxMR Loop Field Usage..................16-43 16-17 Address Multiplexing ..................16-44 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 55

    20-9 Single-Buffer Mode IDMA1 Parameter RAM Map ........... 20-18 20-10 DCMR Field Descriptions (Single-Buffer Mode)..........20-19 21-1 TSA Signals......................21-7 21-2 SIRAM Field Descriptions .................. 21-14 21-3 Example SI RAM Entry Settings for an IDL Bus ..........21-16 MOTOROLA Contents...

  • Page 56

    24-7 SCC HDLC RxBD Status and Control Field Descriptions ........24-9 24-8 SCC HDLC TxBD Status and Control Field Descriptions ......... 24-11 24-9 SCCE/SCCM Field Descriptions ................ 24-12 24-10 HDLC SCCS Field Descriptions ................. 24-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 57

    29-4 Receive Commands ....................29-8 29-5 Transmit Errors...................... 29-8 29-6 Receive Errors ....................... 29-8 29-7 SCC Transparent RxBD Status and Control Field Descriptions ......29-9 29-8 SCC Transparent Tx BD Status and Control Field Descriptions ......29-11 MOTOROLA Contents lvii...

  • Page 58

    I2BRG Field Descriptions ..................32-8 32-4 I2CER/I2CMR Field Descriptions ................ 32-8 32-5 I2COM Field Descriptions ..................32-9 32-6 C Parameter RAM Memory Map ............... 32-9 32-7 RFCR/TFCR Field Descriptions ................. 32-11 32-8 C Transmit/Receive Commands............... 32-11 lviii MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 59

    Interrupt Vector Encodings ................... 35-6 35-3 CICR Field Descriptions ..................35-7 35-4 CIVR Field Descriptions ..................35-10 36-1 DSP Library Functions ..................36-2 36-2 FD Status and Control Bits..................36-4 36-3 DSPx Parameter RAM Memory Map ..............36-6 MOTOROLA Contents...

  • Page 60

    Status/Data Shifted Out of Development Port Shift Register ......37-32 37-13 Debug Instructions/Data Shifted Into Development Port Shift Register..... 37-33 37-14 MPC860-Specific Development Support and Debug SPRs........ 37-36 37-15 Development Support/Debug Registers Protection..........37-37 37-16 CMPAÐCMPD Field Descriptions ..............37-37 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 61

    Integer Store Instructions ..................D-22 D-15 Integer Load and Store with Byte-Reverse Instructions........D-22 D-16 Integer Load and Store Multiple Instructions............D-22 D-17 Integer Load and Store String Instructions............D-23 D-18 Memory Synchronization Instructions ..............D-23 D-19 Floating-Point Load Instructions6................ D-23 MOTOROLA Contents...

  • Page 62

    D-38 XFX-Form ......................D-34 D-39 XFL-Form......................D-34 D-40 XS-Form ....................... D-34 D-41 XO-Form ......................D-34 D-42 A-Form ......................... D-35 D-43 M-Form......................... D-36 D-44 MD-Form......................D-36 D-45 MDS-Form ......................D-37 D-46 Instruction Set Legend..................D-38 lxii MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 63

    About This Book The primary objective of this manual is to help communications system designers build systems using the Motorola MPC860 and to help software designers provide operating systems and user-level applications to take fullest advantage of the MPC860. Although this book describes aspects regarding the PowerPCª architecture that are critical for understanding the MPC860 core, it does not contain a complete description of the architecture.

  • Page 64

    Ñ Chapter 10, ÒInstruction Execution Timing,Ó describes the MPC860 instruction unit, and provides ways to make greatest advantage of its RISC architecture characteristics, such as pipelining and parallel execution. It includes a table of instruction latencies and lists dependencies and potential bottlenecks. lxiv MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 65

    DMA (SDMA) channels on the MPC860 with which the CP implements sixteen virtual SDMA channels. Ñ Chapter 21, ÒSerial Interface,Ó describes the serial interface (SI) in which the physical interface to all SCCs and SMCs is implemented. MOTOROLA About This Book...

  • Page 66

    I/O and allows data to be sent to and from the MPC860 over 8 or 16 parallel data lines with two handshake control signals. Ñ Chapter 34, ÒParallel I/O Ports,Ó describes the four general-purpose I/O lxvi MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 67

    ¥ Appendix C, ÒRegister Quick Reference Guide,Ó contains a quick reference guide to the MPC860 registers. ¥ Appendix D, ÒMPC860 Instruction Set Listings,Ó contains tables of the PowerPC instructions supported by the MPC860. ¥ This manual also includes a glossary and an index. MOTOROLA About This Book lxvii...

  • Page 68

    60x family of PowerPC microprocessors. ¥ PowerPC Microprocessor Family: The ProgrammerÕs Reference Guide (Motorola order #: MPCPRG/D) is a concise reference that includes the register summary, memory control model, exception vectors, and the PowerPC instruction set.

  • Page 69

    In certain contexts, such as in a signal encoding or a bit Þeld, indicates a donÕt care. Used to express an undeÞned numerical value  NOT logical operator & AND logical operator OR logical operator MOTOROLA About This Book lxix...

  • Page 70

    Register used for determining the source of a DSI exception Digital signal processing DTLB Data translation lookaside buffer Effective address EEST Enhanced Ethernet serial transceiver EPROM Erasable programmable read-only memory Floating-point register FPSCR Floating-point status and control register MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 71

    Multiply accumulate MESI ModiÞed/exclusive/shared/invalidÑcache coherency protocol Memory management unit Most-signiÞcant byte Most-signiÞcant bit Machine state register Not a number Next instruction address NMSI Nonmultiplexed serial interface No-op No operation Operating environment architecture Open systems interconnection MOTOROLA About This Book lxxi...

  • Page 72

    SRR0 Machine status save/restore register 0 SRR1 Machine status save/restore register 1 Test access port Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UIMM Unsigned immediate value lxxii MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 73

    Instruction storage interrupt (ISI) ISI exception Interrupt Exception Privileged mode (or privileged state) Supervisor-level privilege Problem mode (or problem state) User-level privilege Real address Physical address Relocation Translation Storage (locations) Memory Storage (the act of) Access MOTOROLA About This Book lxxiii...

  • Page 74

    Table iii. Instruction Field Conventions The Architecture SpeciÞcation Equivalent to: BA, BB, BT crbA, crbB, crbD (respectively) BF, BFA crfD, crfS (respectively) RA, RB, RT, RS rA, rB, rD, rS (respectively) SIMM UIMM /, //, /// 0...0 (shaded) lxxiv MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 75

    Book titles in text are set in italics. PreÞx to denote hexadecimal number PreÞx to denote binary number rA, rB Instruction syntax used to identify a source GPR Instruction syntax used to identify a destination GPR MOTOROLA Part I. Overview...

  • Page 76

    Infrared Data Association ISDN Integrated services digital network ITLB Instruction translation lookaside buffer Integer unit JTAG Joint Test Action Group Least recently used (cache replacement algorithm) Load/store unit Memory management unit Machine state register I-ii MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 77

    Serial peripheral interface Special-purpose register SRAM Static random access memory Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UISA User instruction set architecture User-programmable machine Virtual environment architecture MOTOROLA Part I. Overview I-iii...

  • Page 78

    Part I. Overview I-iv MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 79

    Unless otherwise speciÞed, the PowerQUICC unit is referred to as the MPC860 in this manual. The MPC860 is a PowerPC architecture-based derivative of MotorolaÕs MC68360 Quad Integrated Communications Controller (QUICCª). The CPU on the MPC860 is a 32-bit PowerPC implementation that incorporates memory management units (MMUs) and instruction and data caches.

  • Page 80

    Ñ Software watchdog Ñ Periodic interrupt timer (PIT) Ñ Low-power stop mode Ñ Clock synthesizer Ñ PowerPC decrementer and time base Ñ Real-time clock (RTC) Ñ Reset controller Ñ IEEE 1149.1 test access port (JTAG) MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 81

    Ñ AppleTalk Ñ Universal asynchronous receiver transmitter (UART) Ñ Synchronous UART Ñ Serial infrared (IrDA) Ñ Binary synchronous communication (BISYNC) Ñ Totally transparent (bit streams) Ñ Totally transparent (frame based with optional cyclic redundancy check (CRC)) MOTOROLA Chapter 1. MPC860 Overview...

  • Page 82

    PLL active for fast wake up Ñ Deep sleepÑAll units disabled including PLL except RTC, PIT, time base, and decrementer. Ñ Power down modeÑ All units powered down except PLL, RTC, PIT, time base and decrementer MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 83

    1.2 Architecture Overview The MPC860 integrates an embedded PowerPC core with high-performance, low-power peripherals to extend the Motorola Data Communications family of embedded processors even farther into high-end communications and networking products. The MPC860 is comprised of three modules that each use the 32-bit internal bus: the PowerPC core, the system integration unit (SIU), and the communication processor module (CPM).

  • Page 84

    The core can compare using =, ¹, <, > conditions to generate watchpoints. Each watchpoint can then generate a break point that can be programmed to trigger in a programmable number of events. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 85

    A gear mode is provided which is determined by a clock divider, allowing the operating system to reduce the operational frequency of the processor. Doze mode disables core functional units other MOTOROLA Chapter 1. MPC860 Overview...

  • Page 86

    (MAC) function on the CPM further enhances the MPC860, enabling various modem and DSP applications. Because the CPM architectural approach remains intact between the MPC860 and the MC68360 QUICC, a user of the MC68360 QUICC can easily become familiar with the MPC860. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 87

    CPU commands, address, and serial request which are useful for software debugging. Support for single-step operation with all CPM registers visible further simpliÞes software development for the CPM. MOTOROLA Chapter 1. MPC860 Overview...

  • Page 88

    Part I. Overview 1-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 89

    32 bits 17.4.5/17-12 POR2ÑPCMCIA interface option register 2 32 bits 17.4.6/17-13 PBR3ÑPCMCIA interface base register 3 32 bits 17.4.5/17-12 POR3ÑPCMCIA interface option register 3 32 bits 17.4.6/17-13 PBR4ÑPCMCIA interface base register 4 32 bits 17.4.5/17-12 MOTOROLA Chapter 2. Memory Map...

  • Page 90

    OR6ÑOption register bank 6 32 bits 16.4.2/16-10 BR7ÑBase register bank 7 32 bits 16.4.1/16-8 OR7ÑOption register bank 7 32 bits 16.4.2/16-10 140Ð163 Reserved 36 bytes Ñ MARÑMemory address register 32 bits 16.4.7/16-17 MCRÑMemory command register 32 bits 16.4.5/16-15 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 91

    System Integration Timers Keys TBSCRKÑTimebase status and control register 32 bits 11.4.5/11-11 TBREFAKÑTimebase reference register A key 32 bits 11.4.5/11-11 TBREFBKÑTimebase reference register B key 32 bits 11.4.5/11-11 TBKÑTimebase/decrementer register key 32 bits 11.4.5/11-11 MOTOROLA Chapter 2. Memory Map...

  • Page 92

    32 bits 20.2.4/20-5 SDSRÑSDMA status register 8 bits 20.2.2/20-4 909Ð90B Reserved 3 bytes Ñ SDMRÑSDMA mask register 8 bits 20.2.3/20-5 90DÐ90F Reserved 3 bytes Ñ IDSR1ÑIDMA1 status register 8 bits 20.3.9.2/20-19 911Ð913 Reserved 3 bytes Ñ MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 93

    TMR1ÑTimer 1 mode register 16 bits 18.2.3.2/18-9 TMR2ÑTimer 2 mode register 16 bits 18.2.3.2/18-9 TRR1ÑTimer 1 reference register 16 bits 18.2.3.3/18-10 TRR2ÑTimer 2 reference register 16 bits 18.2.3.3/18-10 TCR1ÑTimer 1 capture register 16 bits 18.2.3.4/18-10 MOTOROLA Chapter 2. Memory Map...

  • Page 94

    Baud Rate Generators BRGC1ÑBRG1 conÞguration register 32 bits 21.4.1/21-40 BRGC2ÑBRG2 conÞguration register 32 bits 21.4.1/21-40 9F8Ð9FF Reserved 8 bytes Ñ SCC1 GSMR_L1ÑSCC1 general mode register 32 bits 22.1.1/22-3 GSMR_H1ÑSCC1 general mode register 32 bits 22.1.1/22-3 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 95

    23.20/23-21 (UART) 24.11/24-12 (HDLC) 26.13.1/26-9 (Asynchronous HDLC) 27.15/27-16 (BISYNC) 29.13/29-13 (Transparent) Reserved 16 bits Ñ SCCM2ÑSCC2 mask register 16 bits 23.20/23-21 (UART) 24.12/24-14 (HDLC) 26.13.3/26-11 (Asynchronous HDLC) 27.15/27-16 (BISYNC) 29.13/29-13 (Transparent) Reserved 8 bits Ñ MOTOROLA Chapter 2. Memory Map...

  • Page 96

    DSR4ÑSCC4 data synchronization register 16 bits 22.1.3/22-10 SCCE4ÑSCC4 event register 16 bits 23.20/23-21 (UART) 24.12/24-14 (HDLC) A72ÐA73 Reserved 2 bytes 26.13.3/26-11 (Asynchronous HDLC) SCCM4ÑSCC4 mask register 16 bits 27.15/27-16 (BiSYNC) 29.13/29-13 (Transparent) Reserved 1 byte Ñ MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 97

    31.4.3/31-10 AAEÐAB1 Reserved 4 bytes Ñ Parallel Interface Port(PIP) PIPCÑPIP conÞguration register 16 bits 33.4.1/33-7 AB4ÐAB5 Reserved 2 bytes Ñ PTPRÑPIP timing parameters register 16 bits 33.4.4/33-10 PBDIRÑPort B data direction register 32 bits 34.3.1.3/34-10 MOTOROLA Chapter 2. Memory Map...

  • Page 98

    Specialized RAM C00ÐDFF SIRAMÑSI routing RAM 21.2.3.7/21-14 bytes E00Ð1FFF Reserved 4,608 Ñ bytes Dual-Ported RAM 2000Ð2FFF DPRAMÑDual-ported RAM 4,096 19.6/19-9 bytes 3000Ð3BFF DPRAMÑDual-ported RAM expansion (reserved) 3,072 Ñ bytes 3C00Ð3FFF PRAMÑParameter RAM 1,024 19.6.3/19-11 bytes 2-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 99

    ¥ Easy to interface to slave devices ¥ Bus is synchronous (all signals are referenced to rising edge of bus clock) ¥ Contains supports for data parity The MPC860 bus interface signals are shown in Figure 3-1. MOTOROLA Chapter 3. Hardware Interface Overview...

  • Page 100

    TxD3/PD10 ALE_B/DSCK/AT1 RxD4/PD9 WAIT_B TxD4/PD8 IP_B[0Ð1]/WP[0Ð1]/VFLS[0Ð1] RTS3/PD7 IP_B2/IOIS16_B /AT2 RTS4/PD6 IP_B3/WP2/VF2 REJECT2 /PD5 IP_B4/LWP0/VF0 REJECT3 /PD4 IP_B5/LWP1/VF1 REJECT4 /PD3 IP_B6/DSDI/AT0 IP_B7/PTR/VAT3 DSDI/TDI OP[0Ð1] DSCK/TCK OP2/MODCK1/STS TRST OP3/MODCK2/DSDO DSDO/TDO BADDR30/REG BADDR[28Ð29] Figure 3-1. MPC860 External Signals MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 101

    Burst TransactionÑThis signal is driven by the bus master to indicate that the current Three-state initiated transfer is a burst. The MPC860 drives this signal when it is bus master. This signal is input when an external master initiates a transaction on the bus. MOTOROLA Chapter 3. Hardware Interface Overview...

  • Page 102

    Interrupt Request 2ÑOne of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 103

    Parity generation and checking is not supported for external masters. Interrupt Request 5ÑOne of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. MOTOROLA Chapter 3. Hardware Interface Overview...

  • Page 104

    BR7 and OR7 in the memory controller. Card Enable 2 Slot BÑThis output enables odd byte transfers when accesses to the PCMCIA Slot B are handled under the control of the PCMCIA interface. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 105

    UPMA when an external transfer to a slave is controlled by UPMA. General-Purpose Line 1 on UPMBÑThis output reßects the value speciÞed in the UPMB when an external transfer to a slave is controlled by UPMB. MOTOROLA Chapter 3. Hardware Interface Overview...

  • Page 106

    PCMCIA Slot A are handled under the control of the PCMCIA interface. CE2_A Output Card Enable 2 Slot AÑThis output enables odd byte transfers when accesses to PCMCIA Slot A are handled under the control of the PCMCIA interface. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 107

    ßow executed by the core. Visible Instruction Queue Flushes StatusÑThe MPC860 outputs VF0 with VF1/VF2 when instruction ßow tracking is required. VFn reports the number of instructions ßushed from the instruction queue in the core. MOTOROLA Chapter 3. Hardware Interface Overview...

  • Page 108

    PCMCIA interface, this signal duplicates the value of TSIZ0/REG. When an external master initiates an access, REG is output by the PCMCIA interface (if it must handle the transfer) to indicate the space in the PCMCIA card being accessed. 3-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 109

    CLK3ÑOne of eight clock inputs that can be used to clock SCCs and SMCs. TIN2ÑTimer 2 external clock input. TIN2 L1TCLKA L1TCLKAÑTransmit clock for the serial interface TDM port A. BRGO2 BRGO2ÑOutput clock of BRG2. MOTOROLA Chapter 3. Hardware Interface Overview 3-11...

  • Page 110

    C serial clock pin. Bidirectional; should be conÞgured as an open-drain BRGO2 Open-drain) output. BRGO2ÑBRG2 output clock. PB[25] Bidirectional General-Purpose I/O Port B Bit 25ÑBit 25 of the general-purpose I/O port B. SMTXD1 (Optional: SMTXD1ÑSMC1 transmit data output. Open-drain) 3-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 111

    Bidirectional General-Purpose I/O Port C Bit 13ÑBit 13 of the general-purpose I/O port C. L1RQB L1RQBÑD-channel request signal for the serial interface TDM port B. L1ST3 L1ST3ÑOne of four output strobes that can be generated by the serial interface. MOTOROLA Chapter 3. Hardware Interface Overview 3-13...

  • Page 112

    Bidirectional General-Purpose I/O Port D Bit 10ÑBit 10 of the general-purpose I/O port D. TXD3 TXD3ÑTransmit data for serial channel 3. PD[9] Bidirectional General-Purpose I/O Port D Bit 9ÑBit 9 of the general-purpose I/O port D. RXD4 RXD4ÑReceive data for serial channel 4. 3-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 113

    VDDSYNÑPower supply of the PLL circuitry. KAPWRÑPower supply of the internal OSCM, RTC, PIT, DEC, and TB. VSSÑGround for circuits, except for the PLL circuitry. VSSSYN, VSSSYN1ÑGround for the PLL circuitry. NOTE: * See Figure 13-2. MOTOROLA Chapter 3. Hardware Interface Overview 3-15...

  • Page 114

    Part I. Overview 3-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 115

    ¥ Chapter 9, ÒMemory Management Unit (MMU)Ó describes how the PowerPC MMU model is implemented on the MPC860. Although the MPC860 MMU is based on the PowerPC MMU model, it differs greatly in many respects, which are described in this chapter. MOTOROLA Part II. PowerPC Microprocessor Module II-i...

  • Page 116

    60x family of PowerPC microprocessors. ¥ PowerPC Microprocessor Family: The ProgrammerÕs Reference Guide (Motorola order #: MPCPRG/D) is a concise reference that includes the register summary, memory control model, exception vectors, and the PowerPC instruction set.

  • Page 117

    Part II. PowerPC Microprocessor Module For a current list of useful Motorola documentation, refer to the world-wide web at http:// www.motorola.com/SPS/RISC/netcomm and at http://www.mot.com/SPS/PowerPC/. Conventions This chapter uses the following notational conventions: Bold entries in Þgures and tables showing registers and parameter Bold RAM should be initialized by the user.

  • Page 118

    Least recently used Least-signiÞcant byte Least-signiÞcant bit Load/store unit Memory management unit Most-signiÞcant byte Most-signiÞcant bit Machine state register Not a number No-op No operation Operating environment architecture Peripheral component interconnect Processor version register II-iv MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 119

    Data storage interrupt (DSI) DSI exception Extended mnemonics SimpliÞed mnemonics Instruction storage interrupt (ISI) ISI exception Interrupt Exception Privileged mode (or privileged state) Supervisor-level privilege Problem mode (or problem state) User-level privilege Real address Physical address MOTOROLA Part II. PowerPC Microprocessor Module II-v...

  • Page 120

    Table vii. Instruction Field Conventions The Architecture SpeciÞcation Equivalent to: BA, BB, BT crbA, crbB, crbD (respectively) BF, BFA crfD, crfS (respectively) RA, RB, RT, RS rA, rB, rD, rS (respectively) SIMM UIMM /, //, /// 0...0 (shaded) II-vi MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 121

    ÒMPC860 Instruction Set.Ó 4.1 PowerPC Architecture Overview The PowerPC architecture, developed jointly by Motorola, IBM, and Apple Computer, is based on the POWERª architecture implemented by RS/6000ª family of computers. The PowerPC architecture takes advantage of recent technological advances in such areas as...

  • Page 122

    ¥ Support for 64-bit addressing. The architecture supports both 32-bit or 64-bit implementations. This document describes the 32-bit portion of the PowerPC architecture. For information about the 64-bit architecture, see PowerPC Microprocessor Family: The Programming Environments. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 123

    UISA and the VEA levels. For a more detailed discussion of the characteristics of the PowerPC architecture, see the Programming Environments Manual. For details regarding the MPC860 as a PowerPC implementation, see Section 4.6, ÒThe MPC860 and the PowerPC Architecture.Ó MOTOROLA Chapter 4. The PowerPC Core...

  • Page 124

    ¥ Power Dissipation Control ¥ Time Base Counter ¥ Decrementer ¥ JTAG 32-Bit ¥ BDM interface 4 Kbyte 4 Kbyte Tags Tags ¥ Clock Multiplier D-Cache I-Cache U-Bus Interface Figure 4-1. Block Diagram of the Core MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 125

    Ñ Load/store unit (LSU)ÑImplements all load and store instructions except ßoating-point load/store instructions. Note that because the MPC860 does not implement ßoating-point load and store instructions, this document refers to integer load/store instructions simply as load/store instructions. MOTOROLA Chapter 4. The PowerPC Core...

  • Page 126

    This information is used to enable out-of-order completion of instructions and ensure a precise exception model. An instruction can be retired after all instructions ahead of it have retired and it updates the architected destination registers without taking an exception. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 127

    To reduce the latency caused by misprediction, PowerPC branch instructions allow the programmer to indicate whether a branch is likely to be taken. This is called static branch prediction. MOTOROLA Chapter 4. The PowerPC Core...

  • Page 128

    PowerPC UISA) determines which instruction stream is prefetched while the branch is being resolved. When the branch operand becomes available, it is forwarded to the BPU and the condition is evaluated. The static branch prediction mechanism is shown in Table 4-1. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 129

    As shown in Figure 4-1, the MPC860 allows parallel execution of instructions using separate branch processing unit (BPU), load/store unit (LSU), and integer unit (IU). These execution units are described in the following sections. MOTOROLA Chapter 4. The PowerPC Core...

  • Page 130

    The following lists the LSUÕs main features: ¥ All instructions implemented in hardware, including unaligned, string, and multiple accesses ¥ Two-entry load/store instruction address queue 4-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 131

    Figure 4-5. LSU Functional Block Diagram To execute multiple/string instructions and unaligned accesses, the LSU increments the EA to access all necessary data. This allows the LSU to execute unaligned accesses without stalling the master instruction pipeline. MOTOROLA Chapter 4. The PowerPC Core 4-11...

  • Page 132

    4.5.3.4 Nonspeculative Load Instructions Load instructions targeted at nonspeculative memory are identiÞed as nonspeculative one clock cycle after the previous load/store bus cycle ends, only if all prior instructions have Þnished without an exception. 4-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 133

    LSU. The external bus interface implements memory reservations as they relate to accesses made by external bus devices. Accesses made by other internal devices to internal memories implement memory reservations as they relate to special internal bus snoop logic. MOTOROLA Chapter 4. The PowerPC Core 4-13...

  • Page 134

    MPC860 (such as TLBs) and some of which are not, such as the eciwx and ecowx instructions. ¥ The PowerPC architecture deÞnes features, such as virtual memory and ßoating-point instructions, that are not implemented on the MPC860. 4-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 135

    For load with update and store with update instructions where rA = 0, the EA is written into r0. For load/store with load with update instructions where rA = rD, rA is boundedly undeÞned. update instructions MOTOROLA Chapter 4. The PowerPC Core 4-15...

  • Page 136

    See Section 4.5.3.5, ÒUnaligned Accesses for a description of integer unaligned instruction execution and timing and to Section 10.2.2, ÒString Instruction Latency,Ó for a description of string instruction timing. 4-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 137

    This memory is part of the main memory as seen by the core but cannot be accessed by any external system device. MOTOROLA Chapter 4. The PowerPC Core 4-17...

  • Page 138

    TLB error exception mechanism when writing to an unmodiÞed page. Memory Two protection modes are supported by the MPC860: protection ¥ Domain manager mode ¥ PowerPC mode See Chapter 9, ÒMemory Management Unit (MMU).Ó 4-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 139

    These are described brießy in Section 5.1.3, ÒMPC860-SpeciÞc SPRs,Ó but are described thoroughly in later chapters. Table 5-9 and Table 2-1 provide cross references to the sections in this book where each register is described. MOTOROLA Chapter 5. PowerPC Core Register Set...

  • Page 140

    The condition register (CR) is a 32-bit register that reßects the result of certain operations and provides a mechanism for testing and branching. The bits in the CR are grouped into eight 4-bit Þelds, CR0ÐCR7, as shown in Figure 5-1. Figure 5-1. Condition Register (CR) MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 141

    5.1.1.1.3 XER Figure 5-2 shows XER bit assignments. Settings are based on the Þnal result produced by executing an instruction. Field Ñ Reset 0000_0000_0000_0000 Field Ñ BCNT Reset 0000_0000_0000_0000 Figure 5-2. XER Register MOTOROLA Chapter 5. PowerPC Core Register Set...

  • Page 142

    SPRs, except for the machine state register (MSR), described in Table 5-5 Table 5-5. Supervisor-Level PowerPC Registers Description Name Comments Serialize Access Machine state register See Section 5.1.2.3.1, ÒMachine State Register Write fetch sync (MSR).Ó MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 143

    For a data MMU error, the data MMU loads the DSISR with error status. For alignment exceptions, the DSISR is loaded with the instruction information as deÞned by the PowerPC architecture. MOTOROLA Chapter 5. PowerPC Core Register Set...

  • Page 144

    The 32-bit machine state register (MSR) is used to conÞgure such parameters as the privilege level, whether translation is enabled, and the endian-mode. It can be read by the mfmsr instruction and modiÞed by the mtmsr, sc, and rÞ instructions. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 145

    1 The processor can execute ßoating-point instructions. (This setting is invalid on the MPC860) Machine check enable 0 Machine check exceptions are disabled. 1 Machine check exceptions are enabled. Ñ Reserved MOTOROLA Chapter 5. PowerPC Core Register Set...

  • Page 146

    5.1.3 MPC860-SpeciÞc SPRs Table 5-2 and Table 5-9 list SPRs speciÞc to the MPC860. Debug registers, which have additional protection, are described in Chapter 37, ÒSystem Development and Debugging.Ó MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 147

    Read Register 0 (MI_RAM0)Ó 11001 10010 MI_RAM1 Section 9.8.13, ÒDMMU RAM Entry Write (as a store) Read Register 1 (MD_RAM1)Ó 11000 11000 MD_CTR Section 9.8.2, ÒDMMU Control Write (as a store) Register (MD_CTR).Ó MOTOROLA Chapter 5. PowerPC Core Register Set...

  • Page 148

    Fetch sync on write 00100 10011 CMPD Fetch sync on write 00100 10100 Fetch sync on write 00100 10101 Fetch sync on write 00100 10110 COUNTA Fetch sync on write 00100 10111 COUNTB Fetch sync on write 5-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 149

    A system reset interrupt occurs when a nonmaskable interrupt is generated either by the software watchdog timer or the assertion of IRQ0. The only registers affected by the system reset interrupt are MSR, SRR0, and SRR1; no other reset activity occurs. Section 7.1.2.1, MOTOROLA Chapter 5. PowerPC Core Register Set 5-11...

  • Page 150

    ¥ LCTRL2ÑCleared. ¥ COUNTA[16Ð31]ÑCleared. ¥ COUNTB[16Ð31]ÑCleared. ¥ ICRÑCleared (no exception occurred). ¥ DER[2,14,28Ð31]ÑSet (all debug-speciÞc exceptions cause debug mode entry). Reset values for memory-mapped registers are provided with individual register descriptions throughout this manual. 5-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 151

    Operands for single-register memory access instructions have the characteristics shown in Table 6-1. (Although not permitted as memory operands, quad words are shown because quad-word alignment is desirable for certain memory operands.) MOTOROLA Chapter 6. MPC860 Instruction Set...

  • Page 152

    ¥ Trap instructionsÑThese instructions are used to test for a speciÞed set of conditions; see Section 6.2.4.4, ÒTrap Instructions,Ó for more information. ¥ Processor control instructionsÑThese instructions are used for synchronizing memory accesses and managing caches and TLBs. For more information, see Sections 6.2.4.5, 6.2.5.1, and 6.2.6.2. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 153

    In future versions of the PowerPC architecture, instruction codings that are now illegal may become assigned to instructions in the architecture, or may be reserved by being assigned to processor-speciÞc instructions. MOTOROLA Chapter 6. MPC860 Instruction Set...

  • Page 154

    Section A.2, ÒInstructions Sorted by Opcode,Ó in the Programming Environments Manual and Section 6.2.1.4, ÒReserved Instruction Class.Ó Notice that extended opcodes for instructions that are defined only for 64-bit implementations are illegal in 32-bit implementations, and vice versa. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 155

    Manual. 6.2.2.1 Memory Addressing A program references memory using the effective (logical) address computed by the processor when it executes a memory access or branch instruction or when it fetches the next sequential instruction. MOTOROLA Chapter 6. MPC860 Instruction Set...

  • Page 156

    ¥ Previous instructions complete execution in the context (privilege, protection, and address translation) under which they were issued. ¥ The instructions following the sc or rÞ instruction execute in the context established by these instructions. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 157

    Note that the categories used in this section correspond to those used in Chapter 4, ÒAddressing Modes and Instruction Set Summary,Ó in The Programming Environments Manual. These categorizations are somewhat arbitrary and are MOTOROLA Chapter 6. MPC860 Instruction Set...

  • Page 158

    (addc. addco addco.) rD,rA,rB Subtract from Carrying subfc (subfc. subfco subfco.) rD,rA,rB Add Extended adde (adde. addeo addeo.) rD,rA,rB Subtract from Extended subfe (subfe. subfeo subfeo.) rD,rA,rB Add to Minus One Extended addme (addme. addmeo addmeo.) rD,rA MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 159

    L = 0. The crfD operand can be omitted if the result of the comparison is to be placed in CR0. Otherwise the target CR Þeld must be speciÞed in the instruction crfD field. MOTOROLA Chapter 6. MPC860 Instruction Set...

  • Page 160

    GPR. See Appendix F, ÒSimplified Mnemonics,Ó in The Programming Environments Manual for a complete list of simpliÞed mnemonics that allows simpler coding of often-used functions such as clearing the leftmost or rightmost 6-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 161

    ¥ Integer load and store string instructions 6.2.4.2.1 Integer Load and Store Address Generation Integer load and store operations generate effective addresses using register indirect with immediate index mode, register indirect with index mode, or register indirect mode. See MOTOROLA Chapter 6. MPC860 Instruction Set 6-11...

  • Page 162

    Load Half Word Algebraic with Update Indexed lhaux rD,rA,rB Load Word and Zero rD,d(rA) Load Word and Zero Indexed lwzx rD,rA,rB Load Word and Zero with Update lwzu rD,d(rA) Load Word and Zero with Update Indexed lwzux rD,rA,rB 6-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 163

    PowerPC system operating with little-endian byte order, these instructions have the effect of loading and storing data in big-endian order. For more information about big-endian and little-endian byte ordering, see ÒByte OrderingÓ in Chapter 3, ÒOperand Conventions,Ó in The Programming Environments Manual. MOTOROLA Chapter 6. MPC860 Instruction Set 6-13...

  • Page 164

    Table 6-11. Integer Load and Store String Instructions Name Mnemonic Syntax Load String Word Immediate lswi rD,rA,NB Load String Word Indexed lswx rD,rA,rB Store String Word Immediate stswi rS,rA,NB Store String Word Indexed stswx rS,rA,rB 6-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 165

    6.2.4.3.1 Branch Instruction Address Calculation Branch instructions can alter the sequence of instruction execution. Instruction addresses are always assumed to be word aligned; the processor ignores the two low-order bits of the generated branch target address. MOTOROLA Chapter 6. MPC860 Instruction Set 6-15...

  • Page 166

    Condition Register NAND crnand crbD,crbA,crbB Condition Register NOR crnor crbD,crbA,crbB Condition Register Equivalent creqv crbD,crbA,crbB Condition Register AND with Complement crandc crbD,crbA,crbB Condition Register OR with Complement crorc crbD,crbA,crbB Move Condition Register Field mcrf crfD,crfS 6-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 167

    See Section 8.6.6, ÒAtomic Memory References,Ó for additional information about these instructions and about related aspects of memory synchronization. Table 6-18 lists the UISA memory synchronization instructions for the MPC860. MOTOROLA Chapter 6. MPC860 Instruction Set 6-17...

  • Page 168

    However, in reality, other processors may have read from the location during this operation. In the MPC860, the reservations are made on behalf of aligned 16-byte sections of the memory address space. 6-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 169

    The PowerPC VEA describes the semantics of the memory model that can be assumed by software processes, and includes descriptions of the cache model, cache control instructions, address aliasing, and other related issues. MOTOROLA Chapter 6. MPC860 Instruction Set 6-19...

  • Page 170

    FIFO's data. This should not be done unless it is certain that the instruction will be completed and not cancelled. The same function as eieio can be accomplished by deÞning a memory space as having the guarded attribute in the MMU, in which case, the eieio instruction is redundant. 6-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 171

    The cache block could be written back as a result of the execution of an instruction that causes a cache miss and the invalid addressed cache block is the target for replacement or a Data Cache Block Store (dcbst) instruction. MOTOROLA Chapter 6. MPC860 Instruction Set 6-21...

  • Page 172

    Table 6-15 lists the instructions provided by the MPC860 for reading from or writing to the MSR. Table 6-21. Move to/from Machine State Register Instructions Name Mnemonic Syntax Move to Machine State Register mtmsr Move from Machine State Register mfmsr 6-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 173

    6.2.6.3.2 Translation Lookaside Buffer Management Instructions Refer to Chapter 9, ÒMemory Management Unit (MMU),Ó for more information about the TLB operations for the MPC860. Table 6-24 lists the TLB instructions. MOTOROLA Chapter 6. MPC860 Instruction Set 6-23...

  • Page 174

    PowerPC architecture should not assume the existence of mnemonics not described in this document. For a complete list of simpliÞed mnemonics, see Appendix F, ÒSimpliÞed Mnemonics,Ó in The Programming Environments Manual. 6-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 175

    ¥ When the exception is taken, the instruction causing the exception might not have started executing, could be partially executed, or has completed, depending on the exception and instruction types. See Table 7-20. For more information, see Section 7.1.4, ÒImplementing the Precise Exception Model.Ó MOTOROLA Chapter 7. Exceptions...

  • Page 176

    SPR Þeld or any SPR encoded as an external SPR if SPR[0] = 1 and MSR[PR] = 1, as well as for attempts to execute supervisor-level instructions when MSR[PR] = 1. See Table 6-11. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 177

    ßushed and additional instruction-related exceptions are handled in order. Typically, asynchronous exceptions are generated by signals or by other hardware conditions. Table 7-2 lists the instruction-related exceptions in the order of detection within the instruction processing. MOTOROLA Chapter 7. Exceptions...

  • Page 178

    Signal from the interrupt controller Decrementer interrupt (masked if MSR[EE] = 0) Decrementer request 7.1.2 PowerPC-DeÞned Exceptions The following sections describe the exceptions as they are deÞned by the OEA, and describes how they are implemented on the MPC860. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 179

    See Chapter 11, ÒSystem Interface Unit,Ó for more details. If MSR[ME] = 1, the machine check interrupt is taken. If SRR1[30] = 1, the interrupt is recoverable. Instruction fetching begins at offset 0x00200 and the registers are set as shown in Table 7-5. MOTOROLA Chapter 7. Exceptions...

  • Page 180

    Þrst instruction that was discarded. If all the instructions in the completion queue were allowed to complete, execution at the end of the exception handler resumes with the next instruction. External MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 181

    For lmw, stmw, lswi, lswx, stswi, and stswx instructions in little-endian mode, an alignment exception always occurs. For lmw and stmw instructions with an operand that is not aligned in big-endian mode, and for lwarx and stwcx. with an operand that is not MOTOROLA Chapter 7. Exceptions...

  • Page 182

    Operations that are not naturally aligned may suffer performance degradation, depending on the processor design, the type of operation, the boundaries crossed, and the mode that the processor is in during execution. More speciÞcally, these operations may either cause MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 183

    Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1. POW 0 Ñ Set to value of ILE Ñ Ñ When a program exception is taken, instruction execution resumes at offset 0x00700 from the physical base address indicated by MSR[IP]. MOTOROLA Chapter 7. Exceptions...

  • Page 184

    A system call exception occurs when a System Call (sc) instruction is executed. The effective address of the instruction following the sc instruction is placed into SRR0. MSR bits are saved in SRR1, as shown in Table 7-10. Then a system call exception is generated. 7-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 185

    Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI]. No change No change Copied from the ILE setting of the interrupted process Others 0 Execution resumes at offset 0x00D00 from the base address indicated by MSR[IP]. MOTOROLA Chapter 7. Exceptions 7-11...

  • Page 186

    This type of exception occurs if MSR[IR] = 1 and an attempt is made to fetch an instruction from a page whose effective page number cannot be translated by TLB. The following registers are set: 7-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 187

    OEA, the concept of segment is retained as the memory space accessible to the level-one table descriptors. ¥ The fetch access violates memory protection. ¥ The fetch access is to guarded memory. MOTOROLA Chapter 7. Exceptions 7-13...

  • Page 188

    Set to the EA of the instruction that caused the exception. SRR1 1Ð4 10Ð15 0 Other Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI]. No change No change Copied from the ILE setting of the interrupted process Others 0 7-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 189

    For L-bus breakpoint conditions. Set to the EA of the data access as computed by the instruction that caused the exception. DSISR For L-bus breakpoint conditions. Do not change. For L-bus breakpoint conditions. Do not change. MOTOROLA Chapter 7. Exceptions 7-15...

  • Page 190

    The following instructions may cause the completion queue to Þll: ¥ Integer divide instructions ¥ Instructions that affect or use resources external to the core (load/store instructions, and especially load/store string multiple/instructions) 7-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 191

    End of critical code segment in which external interrupts were disabled External interrupt disable, but other exception are recoverable: End of handlerÕs prologue, keep external nested interrupts disabled; Start of critical code segment in which external interrupts are disabled Nonrecoverable interrupt: Start of handlerÕs epilogue MOTOROLA Chapter 7. Exceptions 7-17...

  • Page 192

    7.1.6 Exception Latency Figure 7-1 describes signiÞcant events during exception processing. ¥¥¥ Stage Fetch (in IQ) In dispatch entry (IQ0) Execute Complete (In CQ) In retirement entry (CQ0) Instruction Queue Completion Queue Figure 7-1. Exception Latency 7-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 193

    MOTOROLA Chapter 7. Exceptions 7-19...

  • Page 194

    Debug I- breakpoint Before Faulting instruction Debug L- breakpoint Load/store After Faulting instruction + 4 Software emulation Before Faulting instruction Floating-point unavailable Floating-point Before Faulting instruction Implementation-speciÞc exceptions not deÞned by the PowerPC architecture 7-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 195

    ¥ Individual cache blocks can be locked so that frequently accessed instructions and/or data are guaranteed to be resident in the respective cache. On a cache miss, the MPC860Õs cache blocks are Þlled in 16-byte bursts. The burst Þll is MOTOROLA Chapter 8. Instruction and Data Caches...

  • Page 196

    8.1 Instruction Cache Organization The MPC860 instruction cache is organized as 128 sets of two blocks, as shown in Figure 8-1. Each block consists of 16 bytes, a single state bit, a lock bit, and an address tag. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 197

    A[21Ð27] provide the index to select a set, and bits A[28Ð29] select a word within a block. The tags consist of the high-order physical address bits PA[0Ð20]. Address translation occurs in parallel with set selection (from A[21Ð27]). MOTOROLA Chapter 8. Instruction and Data Caches...

  • Page 198

    The MPC860 supports commands for locking and unlocking individual cache blocks and for unlocking all the cache blocks at once. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 199

    Each cache block contains four contiguous words from memory that are loaded from a four-word boundary (that is, bits A[28Ð31] of the logical (effective) addresses are zero); as a result, cache blocks are aligned with page boundaries. Note that address bits A[21Ð27] MOTOROLA Chapter 8. Instruction and Data Caches...

  • Page 200

    (that is, when MSR[PR] = 0). Any attempt to access these SPRs with a user-level program (MSR[PR] = 1) results in a supervisor-level program exception. The IC_CST register, shown in Figure 8-3, has an SPR encoding of 560. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 201

    Error detected Note that this is a read-only, sticky bit, set only by the MPC860 when an error is detected. Reading this bit clears it. CCER3 Instruction cache error type 3Ñreserved. 13Ð31 Ñ Reserved MOTOROLA Chapter 8. Instruction and Data Caches...

  • Page 202

    The instruction cache read command, issued by reading the IC_DAT register, uses the IC_ADR register to qualify what is to be read. Table 8-4 describes the Þelds of the IC_ADR register during an instruction cache read command. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 203

    When disabled, the MPC860 ignores the instruction cache valid bit and operates as if all accesses have caching-inhibited access attributes (that is, all instruction fetches are propagated to the bus as single-beat transactions). Disabling the instruction cache does not MOTOROLA Chapter 8. Instruction and Data Caches...

  • Page 204

    Note that the MPC860 considers all zero-wait-state devices on the internal bus as caching-inhibited. For this reason, software should not perform load & lock cache block operations from these devices on the internal bus. 8-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 205

    ÒByte Ordering,Ó for more information. The mtspr and mfspr instructions are used to access the cache control registers, but they can be accessed only by supervisor-level programs (that is, when MSR[PR] = 0). Any MOTOROLA Chapter 8. Instruction and Data Caches 8-11...

  • Page 206

    See Appendix A, ÒByte Ordering,Ó for more information on MPC860 byte ordering. Note that this is a read-only bit. Any attempt to write to it is ignored. This bit is programmed by issuing the appropriate command in DC_CST[CMD]. Reserved 8-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 207

    9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FIELD RESET Ñ Figure 8-7. Data Cache Address Register (DC_ADR) MOTOROLA Chapter 8. Instruction and Data Caches 8-13...

  • Page 208

    Table 8-9. DC_ADR Fields for Cache Read Commands 0Ð17 21Ð27 28Ð31 Reserved 0 Tags 0 Way 0 Reserved Set select Reserved 1 Way 1 (0Ð127) 1 Copyback Reserved Copyback buffer Reserved buffer address/ data-word select 8-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 209

    & lock cache block and ßush cache block commands. Note that when the data cache is executing a command, it stops handling CPU requests, which can result in machine stalls. MOTOROLA Chapter 8. Instruction and Data Caches 8-15...

  • Page 210

    These bits are set by the MPC860 and are cleared by software. Note that the MPC860 considers all zero-wait-state devices on the internal bus as caching-inhibited. For this reason, software should not perform load & lock operations from these devices on the internal bus. 8-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 211

    DC_CST[CCER1] is set and a machine check exception is generated. The data of the cache block ßagged by the bus error is contained in the copyback buffer; it will have already been MOTOROLA Chapter 8. Instruction and Data Caches 8-17...

  • Page 212

    The MPC860 treats these instructions identically (that is, a dcbtst instruction behaves exactly the same as a dcbt instruction on the MPC860). 8-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 213

    ÒReading Data Cache Tags and Copyback Buffer,Ó for more information. The function of this instruction is independent of the memory/cache access attributes. The dcbst instruction executes regardless of whether the cache is disabled or the cache block is locked. MOTOROLA Chapter 8. Instruction and Data Caches 8-19...

  • Page 214

    PowerPC core. As shown in Figure 8-1, bits 21Ð27 of the instruction address provide the index to select a set (0Ð127) within the instruction cache array. The tags from both ways of the set are compared against bits 0Ð20 of the instruction address. If a 8-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 215

    To minimize power consumption, the MPC860 can detect that one of the buffers contains the requested instruction and service the instruction request from the buffers without activating the instruction cache array. MOTOROLA Chapter 8. Instruction and Data Caches 8-21...

  • Page 216

    Locked cache blocks are never replaced. The instruction cache is not blocked to internal accesses while the fetch (caused by a cache miss) completes. This functionality is sometimes referred to as Ôhits under misses,Õ because 8-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 217

    MOTOROLA Chapter 8. Instruction and Data Caches 8-23...

  • Page 218

    Therefore, software must maintain data cache coherency. The MPC860 does not provide support for snooping external bus activity. All coherency between the internal caches and external agents (memory or I/O devices) must be controlled by 8-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 219

    Þll is waiting to complete. If no bus errors are encountered during the 4-word cache block load, the burst buffer is written to the cache array (provided the cache array is not busy servicing a hit) and the cache block is marked unmodiÞed-valid. MOTOROLA Chapter 8. Instruction and Data Caches 8-25...

  • Page 220

    If the store hit is to a unmodiÞed-valid cache block, then data is stored in the cache block and the block is marked modiÞed-valid. In either case, the LRU state of the set is updated to reßect the hit. 8-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 221

    The PowerPC architecture allows the result of such programming errors to be boundedly undeÞned. Software must ensure that data from a caching-inhibited regions have not been previously loaded into the data cache, or, if they MOTOROLA Chapter 8. Instruction and Data Caches 8-27...

  • Page 222

    If a memory region is marked caching-allowed, the MPC860 assumes that it is the single master in the system to that region. If a caching-allowed lwarx or stwcx. access misses in the data cache, the transaction on the internal and external buses do not have a reservation. 8-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 223

    8.8.1 Instruction and Data Cache Operation in Debug Mode The development system interface of the MPC860 uses the development port, which is a dedicated serial port. The development port is a relatively inexpensive interface that allows MOTOROLA Chapter 8. Instruction and Data Caches 8-29...

  • Page 224

    4. To restore the old state of the LRU bits make sure that the last access (load& lock cache block or unlock cache block command) is performed on the most-recently used way (not the LRU way). 8-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 225

    For the dcbst/dcbf/dcbi instructions, the data cache and memory are updated according to the PowerPC architecture, but the LRU bits in the data cache array are not updated. MOTOROLA Chapter 8. Instruction and Data Caches 8-31...

  • Page 226

    Part II. PowerPC Microprocessor Module 8-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 227

    Ñ Guarded attribute for memory-mapped I/O and other nonspeculative regions ¥ Instruction and data address translation can be disabled separately. ¥ MPC860-speciÞc special-purpose registers (SPRs) accessible with the PowerPC mfspr/mtspr instructions. MOTOROLA Chapter 9. Memory Management Unit (MMU)

  • Page 228

    Ñ Additional registers and exceptions for handling table walks in software. Note that although the MPC860 does not deÞne segment registers as they are deÞned by the OEA, the concept of segment is retained as the memory space accessible to the level-one table descriptors. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 229

    (EPN) overlaps one in the TLB (when taking into account pages sizes, subpage validity ßags, user/supervisor state, address pace ID (ASID), and the SH values of the TLB entries), the new EPN is written and the old one is invalidated. MOTOROLA Chapter 9. Memory Management Unit (MMU)

  • Page 230

    DMMU does not implement a fast TLB mechanism. The DTLB is accessed for each transfer simultaneously with the data cache tag read, hence there is no time penalty. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 231

    CASID are provided to the TLB, as shown in Figure 9-3. In the TLB, the EA and CASID are compared with each entryÕs EPN and ASID. The CASID is compared only when the matching entry is programmed as unshared. See Table 9-11 and Table 9-12. MOTOROLA Chapter 9. Memory Management Unit (MMU)

  • Page 232

    Mx_AP Þelds to 01. In PowerPC mode, each Þeld holds the Kp and Ks bits for the corresponding segment deÞned by the level-one table descriptor. In domain manager mode, each Þeld holds override information over the page protection settingÑno override, no access override, and free access override. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 233

    4-Kbyte pages differ. ¥ Mode 3ÑProtection resolution to 1-Kbyte minimum subpage size, with no restriction on subpage mapping. In this mode, set: Ñ MD_CTR[TWAM] = 0 Ñ Mx_CTR[PPM] = 0 Ñ Mx_CTR[PPC5] = 0 MOTOROLA Chapter 9. Memory Management Unit (MMU)

  • Page 234

    Therefore, attempting to write to a page marked unmodiÞed invalidates that entry and causes an implementation-speciÞc DTLB error exception. If change bits are not needed, set the C bit to one by default in the PTEs. MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 235

    9.7 Translation Table Structure The MMU hardware supports a two-level software tablewalk. Other table structures are not precluded. Figure 9-4 shows the two-level translation table when MD_CTR[TWAM] = 1 (4-Kbyte resolution of protection). MOTOROLA Chapter 9. Memory Management Unit (MMU)

  • Page 236

    M_TWB. EA[0Ð9] indicates the level-one page descriptor. As shown in Table 9-1, an 8-Mbyte page requires two identical entries in the level-one table, one for bit 9 = 0 and one for bit 9 = 1. 9-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 237

    10Ð19 to Þnd the level-two page descriptor. For pages larger than 4 Kbytes, the entry in the level-two table must be duplicated according to page size, as shown in Table 9-1. MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-11...

  • Page 238

    M_TWB. The level-one table is indexed by EA[0Ð11] to get the level-one page descriptor. For 8-Mbyte pages, there must be eight identical entries in the level-one table for EA[9Ð11]. 9-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 239

    11 8 Kbyte 10 Reserved Writethrough attribute for entry 0 Copyback cache policy region (default) 1 Writethrough cache policy region Level-one segment valid bit 0 Segment is not valid 1 Segment is valid MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-13...

  • Page 240

    The PowerPC tlbie and tlbia instructions can be used to invalidate TLBs. MMU registers should be accessed when both MSR[IR] = 0 and MSR[DR] = 0. No similar restriction exists for tlbie and tlbia. 9-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 241

    9.8.12.2 MI_RAM1 IMMU RAM entry read register 1 9.8.12.3 MD_CAM DMMU CAM entry read register 9.8.12.4 MD_RAM0 DMMU RAM entry read register 0 9.8.12.5 MD_RAM1 DMMU RAM entry read register 1 9.8.13 MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-15...

  • Page 242

    Reserved. Ignored on write. Returns 0 on read. 19Ð23 ITLB_INDX ITLB index. Points to the ITLB entry to be loaded. Decremented every ITLB update 24Ð31 Ñ Reserved. Ignored on write. Returns 0 on read. 9-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 243

    Reserved. Ignored on write. Returns 0 on read 19Ð23 DTLB_INDX DTLB index. Points to DTLB entry to be loaded. Decremented every DTLB update. 24Ð31 Ñ Reserved. Ignored on write. Returns 0 on read MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-17...

  • Page 244

    M_CASID on a TLB miss. 9.8.4 IMMU Tablewalk Control Register (MI_TWC) The IMMU tablewalk control register (MI_TWC), shown in Figure 9-9, contains the access protection group and page size of the entry to be loaded into the TLB. 9-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 245

    9.8.5 DMMU Tablewalk Control Register (MD_TWC) The DMMU tablewalk control register (MD_TWC), shown in Figure 9-10, contains the level-two pointer and access protection group of an entry to be loaded into the TLB. MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-19...

  • Page 246

    The IMMU real page number register (MI_RPN), shown in Figure 9-11, contains the physical address and the memory attributes of an entry to be loaded into a TLB. MI_RPN should be written after MI_EPN and MI_TWC are written. 9-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 247

    0 This entry matches only if ASID Þeld in the TLB entry matches the value M_CASID. 1 ASID comparison is disabled for the entry. Cache-inhibit attribute for the entry. Entry valid indication. MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-21...

  • Page 248

    0100 Hit only for user accesses Resolution ModesÓ). Otherwise, set 1100 Hit for both to 0b1111. Small page size: Clear. Small page size. Valid only when L1 descriptor[PS] = 00 0 4 Kbyte 1 16 Kbyte 9-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 249

    0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field Ñ CASID Reset Ñ Figure 9-14. MMU Current Address Space ID Register (M_CASID) MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-23...

  • Page 250

    0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reset Ñ Figure 9-16. MMU Tablewalk Special Register (M_TW) 9-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 251

    Address space ID of the DTLB entry to be compared with M_CASID[CASID] Shared page 0 This entry matches only if the ASID Þeld in the DTLB entry matches the value in M_CASID. 1 ASID comparison is disabled for the entry MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-25...

  • Page 252

    20Ð22 PS_B Page size. (Values not shown are reserved) 000 4 Kbyte 001 16 Kbyte 011 512 Kbyte 111 8 Mbyte Cache-inhibit attribute for the entry 24Ð27 APG Access protection group. Up to 16 protection groups supported (uses oneÕs complement format) 9-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 253

    0 Subpage 2 (Address[20Ð21] = 10) User fetch is not permitted 1 Subpage 2 (Address[20Ð21] = 10) User fetch is permitted 0 Subpage 3 (Address[20Ð21] = 11) User fetch is not permitted 1 Subpage 3 (Address[20Ð21] = 11) User fetch is permitted MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-27...

  • Page 254

    0 Subpage 2 (address[20Ð21] = 10) is not valid 1 Subpage 2 (address[20Ð21] = 10) is valid 0 Subpage 3 (address[20Ð21] = 11) is not valid 1 Subpage 3 (address[20Ð21] = 11) is valid 9-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 255

    011 512 Kbyte 111 8 Mbyte 23Ð26 APGI Access protection group inverted. Access protection group number in oneÕs complement format Guarded memory attribute for the entry 0 Nonguarded memory 1 Guarded memory MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-29...

  • Page 256

    Software should take an appropriate action before setting this bit to 1. 1 Changed region. Write access is allowed to this page. Entry valid ßag 0 Entry is invalid 1 Entry is valid 9-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 257

    1 Subpage 3 (address[20Ð21] = 11) User read access is permitted UWP3 0 Subpage 3 (address[20Ð21] = 11) User write access is not permitted 1 Subpage 3 (address[20Ð21] = 11) User write access is permitted MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-31...

  • Page 258

    ¥ The level-two pointer is generated when an mfspr[MD_TWC] is performed by concatenating the level-two table base (extracted from the level-one table) with the level-two index. 9-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 259

    9.10.2 Locking TLB Entries Four entries in each TLB can be made unavailable to the replacement algorithm, thus enabling the user to lock translation entries into them by specially conÞguring the TLB replacement counters. MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-33...

  • Page 260

    The ASID value in the entry is ignored for the purpose of matching an invalidate address, thus multiple entries can be invalidated if they have the same effective address and different ASID values. 9-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 261

    MI_CTR[ITLB_INDX], negating MD_EPN[EV] or MI_EPN[EV], and writing to the appropriate MD_RPN or MI_RPN. The TLBs are not invalidated automatically on reset, but are disabled. However, they must be invalidated under program control during initialization. MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-35...

  • Page 262

    Part II. PowerPC Microprocessor Module 9-36 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 263

    The example in Section 10.1.3, ÒPrivate Writeback Bus Load,Ó has no such dependency. r12,64 (SP) r3,r12,3 addic r4,r14,1 mulli r5,r3,3 addi r4,3(r0) MOTOROLA Chapter 10. Instruction Execution Timing 10-1...

  • Page 264

    GCLK1 Fetch mulli addic Decode mulli addic Read + Execute mulli sub, mulli addic addic Writeback mulli Figure 10-3. Writeback Arbitration TimingÑExample 2 10-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 265

    GCLK1 Fetch addic Decode Read + Execute Bubble Bubble Bubble Bubble Writeback L Address Drive L Data Cache Address Load Writeback E Address E Data Figure 10-5. External Load Timing MOTOROLA Chapter 10. Instruction Execution Timing 10-3...

  • Page 266

    BPU allows the two bubbles caused by the bl issue and execution to overlap the two bubbles caused by the load. Issuing bl causes a bubble because it does no work. r12,64 (SP) r3,r12,3 addic r4,r14,1 func func: mulli r5,r3,3 addi r4,3(r0) 10-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 267

    Decode cmpi addic mulli Read + Execute Bubble Bubble cmpi addic mulli Writeback addic L Address Drive L Data Load Writeback Branch Decode Branch Execute Branch Final Decision Figure 10-8. Branch Prediction Timing MOTOROLA Chapter 10. Instruction Execution Timing 10-5...

  • Page 268

    Integer store: stb, stbu, stbx, stbux, sth, sthu, sthx, sthux, stw, stwu, stwbrx, stwx, stwux, sthbrx Integer load/store multiple: lmw, smw Serialize + 1 + no. of registers LSU Synchronize: sync Serialize + 1 10-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 269

    1 cycle 1 cycle 2 cycles 5 cycles Load/store multiple 1 + N 1 + N æ ö æ ö -------------- -------------- è ø è ø N denotes the number of registers transferred. MOTOROLA Chapter 10. Instruction Execution Timing 10-7...

  • Page 270

    See Section 5.1.3.1, ÒAccessing SPRs.Ó If the access ends in a bus error, a software emulation exception is taken. All write operations to off-core SPRs (mtspr) are previously synchronized. In other words, the instruction is not taken until all prior instructions terminate. 10-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 271

    ¥ Chapter 12, ÒReset,Ó describes the behavior of the MPC860 at reset and start-up. Suggested Reading Supporting documentation for the MPC860 can be accessed through the world-wide web at http://www.motorola.com/SPS/RISC/netcomm and at http://www.mot.com/SPS/ PowerPC/. This documentation includes technical speciÞcations, reference materials, and detailed applications notes.

  • Page 272

    Decrementer register Direct memory access DRAM Dynamic random access memory DTLB Data translation lookaside buffer Effective address General-purpose register IEEE Institute of Electrical and Electronics Engineers ITLB Instruction translation lookaside buffer Least-signiÞcant byte Least-signiÞcant bit III-ii MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 273

    Meaning Load/store unit Memory management unit Most-signiÞcant byte Most-signiÞcant bit Machine state register Peripheral component interconnect RISC Reduced instruction set computing RTOS Real-time operating system Receive Special-purpose register Time base register Translation lookaside buffer Transmit MOTOROLA Part III. Configuration III-iii...

  • Page 274

    Part III. Configuration III-iv MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 275

    PCMCIA sockets with a maximum of eight memory or I/O windows. 11.1 Features The following is a list of the SIUÕs main features: ¥ System conÞguration and protection ¥ System interrupt conÞguration ¥ System reset monitoring and generation ¥ Clock synthesizer MOTOROLA Chapter 11. System Interface Unit 11-1...

  • Page 276

    The associated bit in the timebase status and control register (TBSCR) is set for the reference register that generated the interrupt. The timebase is clocked by the TMBCLK clock. 11-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 277

    11.3 Multiplexing SIU Pins Due to the limited number of pins available in the MPC860 package, some of the functionalities share pins. Table 11-1 shows how the functionality is controlled on each pin. MOTOROLA Chapter 11. System Interface Unit 11-3...

  • Page 278

    Using mfspr, software can read IMMR to determine the location and availability of any on-chip system resource. ISB can be written by mtspr, but PARTNUM and MASKNUM are mask programmed and cannot be changed. 11-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 279

    MPC860. Intended to help factory test and user code that is sensitive to part reÞnements. For the latest documentation on part/revision numbers and microcode REV_NUMs, see the website at http://www.motorola.com/SPS/RISC/netcomm/. 11.4.2 SIU Module ConÞguration Register (SIUMCR) The SIU module conÞguration register (SIUMCR) contains bits that conÞgure the following features in the SIU: ¥...

  • Page 280

    Hardware SpeciÞcations for more information.) This bit is locked by the DLK bit. 0 Disable show cycles for all internal data cycles. 1 Show address and data of all internal data cycles. 11-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 281

    11 ALE_B/DSCK/AT1 functions as DSCK IP_B6/DSDI/AT0 functions as DSDI OP3/MODCK2/DSDO functions as DSDO IP_B7/PTR/AT3 functions as PTR TCK/DSCK functions as TCK TDI/DSDI functions as TDI TDO/DSDO functions as TDO Ñ Reserved, should be cleared. MOTOROLA Chapter 11. System Interface Unit 11-7...

  • Page 282

    Bank 2 double drive. If this bit is set, CS2 is reßected on GPL_x2. B3DD Bank 3 double drive. If this bit is set, CS3 is reßected on GPL_x3. 28Ð31 Ñ Reserved, should be cleared. 11-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 283

    0 The software watchdog timer causes an NMI (system reset interrupt) to the core. 1 The software watchdog timer causes an HRESET (default). Software watchdog prescale. 0 The software watchdog timer is not prescaled. 1 The software watchdog timer is prescaled by a factor of 2,048. MOTOROLA Chapter 11. System Interface Unit 11-9...

  • Page 284

    28Ð31 DPB[0Ð3] Data parity error on bytes 0Ð3. Each byte lane has four parity error status bits; one is set for the byte that had a parity error when an internal master requested a data load. Parity checking for memory not controlled by the memory controller is enabled by SIUMCR[PNCS], see Table 11-3. 11-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 285

    (including reads or writes of any other value) to a key register will lock its associated SIU register. For example, writing a 0x55CCAA33 to the RTCK key register allows the RTC register to be written. The key registers are write-only; a read of the MOTOROLA Chapter 11. System Interface Unit 11-11...

  • Page 286

    Module ConÞguration Register (SIUMCR).Ó 11.5.1 Interrupt Structure The SIU receives interrupts from internal sources, like the PIT, real-time clock, communications processor module (CPM), and the external IRQ pins. Figure 11-7 shows the MPC860 interrupt structure. 11-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 287

    Chapter 35, ÒCPM Interrupt Controller.Ó Section 11.5.3.1, ÒNonmaskable InterruptsÑIRQ0 and SWT,Ó describes how IRQ0 operates differently from other IRQ signals, and how the operation is conÞgurable through SIU registers. MOTOROLA Chapter 11. System Interface Unit 11-13...

  • Page 288

    IRQ3 0001_1000 Internal Level 3 0001_1100 IRQ4 0010_0000 Internal Level 4 0010_0100 IRQ5 0010_1000 Internal Level 5 0010_1100 IRQ6 0011_0000 Internal Level 6 0011_0100 IRQ7 0011_1000 Lowest Internal Level 7 0011_1100 16-31 Reserved Ñ 11-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 289

    Figure 11-9 is a logical representation of IRQ0. SIEL[ED0] SIEL[ED0] Level Level IRQ0 Edge Edge SIPEND[IRQ0] SIPEND[IRQ0] Figure 11-9. IRQ0 Logical Representation Table 11-8 describes the differences between IRQ0 and other IRQ interrupts. MOTOROLA Chapter 11. System Interface Unit 11-15...

  • Page 290

    ¥ If an IRQ pin is deÞned as an edge interrupt, the corresponding bit being set indicates that a falling edge was detected on the line. These bits are reset by writing ones to them. 11-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 291

    Field LVM3 IRM LVM4 IRM LVM6 IRM LVM7 Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x014 Field Ñ Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x016 Figure 11-11. SIU Interrupt Mask Register (SIMASK) MOTOROLA Chapter 11. System Interface Unit 11-17...

  • Page 292

    ED0 WM0 ED1 WM1 ED2 WM2 ED3 WM3 ED4 WM4 ED5 WM5 ED6 WM6 ED7 WM7 Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x018 Field Ñ Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x018 Figure 11-12. SIU Interrupt Edge/Level Register (SIEL) 11-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 293

    (branch). The interrupt code is the interrupt number times 4, which allows indexing into the table. When read as a half word, each entry can contain a full routine of up to 256 instructions; see Figure 11-14 and Table 11-7. MOTOROLA Chapter 11. System Interface Unit 11-19...

  • Page 294

    (TS), the monitor begins counting and stops when transfer acknowledge (TA), retry (RETRY) or transfer error (TEA) is asserted. For burst cycles, this action is also performed between subsequent TA assertions for each data beat. If the monitor times out, 11-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 295

    16-bit down-counter clocked by the system clock. When necessary, an additional divide by 2,048 prescaler is used. After the timer reaches 0x0, a software watchdog expiration request is issued to the reset or NMI control logic. At reset, MOTOROLA Chapter 11. System Interface Unit 11-21...

  • Page 296

    0xAA39 should be written to this register. The SWSR can be written at any time, but returns all zeros when read. Field Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x00E Figure 11-17. Software Service Register (SWSR) 11-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 297

    Control of the decrementer is provided in the TBSCR. The decrementer and timebase use TMBCLK. Note that DEC is a keyed register. It must be unlocked in TBK before it can be written. MOTOROLA Chapter 11. System Interface Unit 11-23...

  • Page 298

    Figure 11-19 shows TBU. Note that the TBU and TBL are keyed registers. They must be unlocked in TBK before they can be written. É Field Reset Ñ 269 (Read)/285 (Write) Figure 11-19. Timebase Upper Register (TBU) 11-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 299

    TBREFA (IMMR & 0xFFFF0000) + 0x204/TBREFB (IMMR & 0xFFFF0000) + 0x208 Field TBREFA/TBREFB Reset Ñ Addr TBREFA (IMMR & 0xFFFF0000) + 0x206/TBREFB (IMMR & 0xFFFF0000) + 0x20A Figure 11-21. Timebase Reference Registers (TBREFA and TBREFB) MOTOROLA Chapter 11. System Interface Unit 11-25...

  • Page 300

    REFBE Timebase freeze enable 0 The timebase and decrementer are unaffected. 1 The FRZ signal stops the timebase and decrementer. Timebase enable 0 Disables timebase and decrementer operation. 1 Enables timebase and decrementer operation. 11-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 301

    RTCSC is a keyed register. It must be unlocked in RTCSCK before it can be written. Field RTCIRQ SEC ALR Ñ RTF RTE Reset 0000_0000 Ñ Ñ Addr (IMMR & 0xFFFF0000) + 0x220 Figure 11-24. Real-Time Clock Status and Control Register (RTCSC) Table 11-20 describes RTCSC Þelds. MOTOROLA Chapter 11. System Interface Unit 11-27...

  • Page 302

    (IMMR & 0xFFFF0000) + 0x226 Figure 11-25. Real-Time Clock Register (RTC) Table 11-21 describes the RTC. Table 11-21. RTC Field Description Bits Name Description 0Ð31 RTC Real-time clock. Represents time measured in seconds. Each unit represents one second. 11-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 303

    MHz/512 or 32.768 KHz/4). RTSEC resets at 8192 and increments RTC. Thus, RTC contains the time in seconds and RTSEC functions as a divider. For a 38.4-KHz crystal (instead of 32.768 KHz), RTCSC[38K] should be set to make RTSEC reset at 9600 instead of 8192. 11-29 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 304

    PITC. If the PTE bit is not set, the PIT is unable to count and retains the old count value. Reading the PIT does not affect it. 11-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 305

    Note that PISCR is a keyed register. It must be unlocked in PISCRK before it can be written. Field PIRQ Ñ PIE PITF PTE Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x240 Figure 11-29. Periodic Interrupt Status and Control Register (PISCR) MOTOROLA Chapter 11. System Interface Unit 11-31...

  • Page 306

    Table 11-25 describes PITC Þelds. Table 11-25. PITC Field Descriptions Bits Name Description 0Ð15 PITC PIT count. Contains the count for the periodic timer. Setting this Þeld to 0xFFFF selects the maximum count period. 11-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 307

    This is controlled by the associated bits in the control register of each timer. If they are programmed to stop counting when FRZ is asserted, the counters maintain their values until FRZ is negated. The bus monitor, however, will be enabled regardless of this signalÕs state. MOTOROLA Chapter 11. System Interface Unit 11-33...

  • Page 308

    The PIT, decrementer, and timebase are not inßuenced by these low-power modes and they continue to run at their respective frequencies. These timers can generate an interrupt to bring the MPC860 out of the low-power modes. 11-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 309

    The MPC860 has several sources of input to the reset logic: ¥ Power-on reset ¥ External hard reset ¥ Internal hard reset Ñ Loss of lock Ñ Software watchdog reset Ñ Checkstop reset Ñ Debug port hard reset ¥ JTAG reset MOTOROLA Chapter 12. Reset 12-1...

  • Page 310

    HRESET and SRESET signals. Following the negation of HRESET and SRESET a 16-cycle period passes before an external hard or soft reset will be sampled. Note that external pull-up resistors should be provided to drive the 12-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 311

    See Section 37.3.2.1.2, ÒDevelopment Serial Data In (DSDI).Ó 12.1.5 JTAG Reset When the JTAG logic asserts the JTAG reset signal, an internal soft reset sequence will be generated. MOTOROLA Chapter 12. Reset 12-3...

  • Page 312

    SRESET signal. After 512 cycles the core negates the SRESET signal and the debug port conÞguration is sampled from the DSDI and DSCK signals. Once the core negates SRESET 16 clock cycles must elapse before the external soft reset signal is sampled. 12-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 313

    Figure 12-3. Reset Status Register (RSR) The RSR bits are described in Table 12-2. Note that the bits in this register (except those that are reserved) are negated by writing 1; writing 0 has no effect. MOTOROLA Chapter 12. Reset 12-5...

  • Page 314

    MPC860 using hard and soft reset events. 12.3.1 Hard Reset When a hard reset event occurs, the MPC860 determines its initial mode of operation by sampling the values present on the data bus (D[0Ð31]) or from an internal default constant 12-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 315

    Figure 12-5 shows a reset operation with a short PORESET signal assertion. Note that the conÞguration of the MPC860 is determined from the signal levels driven on the D[0Ð31] signals following the assertion of RSTCONF and the negation of HRESET. MOTOROLA Chapter 12. Reset 12-7...

  • Page 316

    Figure 12-5. Reset Configuration Sampling for Short PORESET Assertion Figure 12-6 shows a reset operation with a long PORESET signal assertion. CLKOUT PORESET INTPORESET HRESET RSTCONF TSUP D[0:31] Default RSTCONF Controlled Figure 12-6. Reset Configuration Sampling for Long PORESET Assertion 12-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 317

    IIP is cleared (default), the MSR[IP] initial value is one; if it is set to one, the MSR[IP] initial value is zero. See Section 5.1.2.3.1, ÒMachine State Register (MSR).Ó 2Ð3 Ñ Reserved for future use and should be allowed to ßoat. MOTOROLA Chapter 12. Reset 12-9...

  • Page 318

    IP_B3/IWP2/VF2 functions as VF2 IP_B4/LWP0/VF0 functions as VF0 IP_B5/LWP1/VF1 functions as VF1 OP2/MODCK1/STS functions as STS ALE_B/DSCK/AT1 functions as AT1 IP_B2/AT2 functions as AT2 IP_B6/DSDI/AT0 functions as AT0 IP_B7/PTR/AT3 functions as AT3 OP3/MODCK2/DSDO functions as OP3 12-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 319

    Reserved. This bit is reserved for future use and should be allowed to ßoat. 12.3.2 Soft Reset When a soft reset event occurs, the MPC860 reconÞgures the development port. See Section 37.3.1.2, ÒEntering Debug Mode,Ó and Section 37.3.2.3.3, ÒSelection of Development Port Clock Mode.Ó MOTOROLA Chapter 12. Reset 12-11...

  • Page 320

    Part III. Configuration 12-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 321

    (GPCM) and a pair of user-programmable machines (UPMs). ¥ Chapter 17, ÒPCMCIA Interface,Ó describes the PCMCIA host adapter module, which provides all control logic for a PCMCIA socket interface and requires only additional external analog power switching logic and buffering. MOTOROLA Part IV. Hardware Interface IV-i...

  • Page 322

    The PowerPC documentation is organized in the following types of documents: ¥ PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors (Motorola order #: MPCBUSIF/AD) provides a detailed functional description of the 60x bus interface, as implemented on the PowerPC 601ª, 603, and 604 family of PowerPC microprocessors.

  • Page 323

    High-level data link control Inter-integrated circuit Inter-chip digital link IEEE Institute of Electrical and Electronics Engineers IrDA Infrared Data Association ISDN Integrated services digital network JTAG Joint Test Action Group LIFO Last-in-Þrst-out Least recently used Least-signiÞcant byte MOTOROLA Part IV. Hardware Interface IV-iii...

  • Page 324

    Systems network architecture. Serial peripheral interface Special-purpose register SRAM Static random access memory Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UISA User instruction set architecture User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter IV-iv MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 325

    Part IV. Hardware Interface MOTOROLA Part IV. Hardware Interface IV-v...

  • Page 326

    Part IV. Hardware Interface IV-vi MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 327

    Chapter 13 External Signals This chapter contains descriptions of the MPC860 input and output signals, showing multiplexing, pin assignments, and reset values. Figure 13-1 shows the signals grouped by function. MOTOROLA Chapter 13. External Signals 13-1...

  • Page 328

    ALE_B/DSCK/AT1 RxD4/PD9 WAIT_B TxD4/PD8 IP_B[0Ð1]/WP[0Ð1]/VFLS[0Ð1] RTS3/PD7 IP_B2/IOIS16_B /AT2 RTS4/PD6 IP_B3/WP2/VF2 REJECT2 /PD5 IP_B4/LWP0/VF0 REJECT3 /PD4 IP_B5/LWP1/VF1 REJECT4 /PD3 IP_B6/DSDI/AT0 IP_B7/PTR/VAT3 DSDI/TDI OP[0Ð1] DSCK/TCK OP2/MODCK1/STS TRST OP3/MODCK2/DSDO DSDO/TDO BADDR30/REG BADDR[28Ð29] Figure 13-1. MPC860 External Signals 13-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 329

    1ÐV17 TxD4/PD8 1ÐW17 RTS3/PD7 1ÐT15 RTS4/PD6 1ÐV16 REJECT2 /PD5 1ÐU15 REJECT3 /PD4 1ÐU16 REJECT4 /PD3 1ÐW16 1ÐG18 DSDI/TDI 1ÐH17 DSCK/TCK 1ÐH16 TRST 1ÐG19 DSDO/TDO 1ÐG17 1ÐL3 Figure 13-2. Signals and Pin Numbers (Part 1) MOTOROLA Chapter 13. External Signals 13-3...

  • Page 330

    R4Ð1 IP_B[0Ð1]/WP[0Ð1]/VFLS[0Ð1] H2, J3Ð2 J2Ð1 IP_B2/IOIS16_B /AT2 G1Ð1 IP_B3/WP2/VF2 G2Ð1 IP_B4/LWP0/VF0 J4Ð1 IP_B5/LWP1/VF1 K3Ð1 IP_B6/DSDI/AT0 H1Ð1 IP_B7/PTR/VAT3 L4, L2Ð2 OP[0Ð1] L1Ð1 OP2/MODCK1/STS M4Ð1 OP3/MODCK2/DSDO BADDR30/REG BADDR[28Ð29] Figure 13-3. Signals and Pin Numbers (Part 2) 13-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 331

    The MPC860 samples TS when it is not the external bus master to allow the memory controller/PCMCIA interface to control the accessed slave device. It indicates that an external synchronous master initiated a transaction. MOTOROLA Chapter 13. External Signals 13-5...

  • Page 332

    (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal sent to the interrupt controller is the logical AND of CR/IRQ3 (if deÞned as IRQ3) and DP0/IRQ3 if deÞned as IRQ3. 13-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 333

    (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal sent to the interrupt controller is the logical AND of this line (if deÞned as IRQ6) and the FRZ/IRQ6 (if deÞned as IRQ6). MOTOROLA Chapter 13. External Signals 13-7...

  • Page 334

    BR7 and OR7 in the memory controller. Card Enable 2 Slot BÑThis output enables odd byte transfers when accesses to the PCMCIA Slot B are handled under the control of the PCMCIA interface. 13-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 335

    UPMB, as programmed by the user. For read or writes, asserted only if their corresponding data lanes contain valid data: BS_A0 for D[0Ð7], BS_A1 for D[8Ð15], BS_A2 for D[16Ð23], BS_A3 for D[24Ð31] MOTOROLA Chapter 13. External Signals 13-9...

  • Page 336

    When RSTCONF is negated, the MPC860 uses the default conÞguration mode. Note that the initial base address of internal registers is determined in this sequence. 13-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 337

    I/O region in socket A of the PCMCIA space. IP_A[3Ð7] Hi-Z W2, U4, U5, Input Input Port A 3-7ÑThe MPC860 monitors these inputs; their T6, T3 values and changes are reported in the PIPR and PSCR of the PCMCIA interface. MOTOROLA Chapter 13. External Signals 13-11...

  • Page 338

    ßow executed by the core. Visible Instruction Queue Flushes StatusÑThe MPC860 outputs VF0 with VF1/VF2 when instruction ßow tracking is required. VFn reports the number of instructions ßushed from the instruction queue in the core. 13-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 339

    PGCRB register in the PCMCIA DSDO interface. Mode Clock 2ÑThis input is sampled at the PORESET negation to conÞgure the PLL/clock mode of operation. Development Serial Data OutputÑOutput data from the debug port interface. MOTOROLA Chapter 13. External Signals 13-13...

  • Page 340

    PA[11] Hi-Z Bidirectional General-Purpose I/O Port A Bit 11ÑBit 11 of the L1TXDB (Optional: general-purpose I/O port A. RXD3 Open-drain) L1TXDBÑTransmit data output for the serial interface TDMb. RXD3 ÑReceive data input for SCC3. 13-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 341

    CLK6ÑOne of eight clock inputs that can be used to clock the L1RCLKB SCCs and SMCs. BRGCLK2 TOUT3ÑTimer 3 output. L1RCLKBÑReceive clock for the serial interface TDMb. BRGCLK2ÑOne of the two external clock inputs of the BRGs. MOTOROLA Chapter 13. External Signals 13-15...

  • Page 342

    SMTXD1 (Optional: general-purpose I/O port B. Open-drain) SMTXD1ÑSMC1 transmit data output. PB[24] Hi-Z Bidirectional General-Purpose I/O Port B Bit 24ÑBit 24 of the SMRXD1 (Optional: general-purpose I/O port B. Open-drain) SMRXD1ÑSMC1 receive data input. 13-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 343

    I/O port B. BRGO3ÑBRG3 output clock. PB[14] Hi-Z Bidirectional General-Purpose I/O Port B Bit 14ÑBit 14 of the RSTRT1 general-purpose I/O port B. RSTRT1ÑSCC1 serial CAM interface outputs that marks the start of a frame. MOTOROLA Chapter 13. External Signals 13-17...

  • Page 344

    Ethernet. PC[6] Hi-Z Bidirectional General-Purpose I/O Port C Bit 6ÑBit 6 of the general-purpose I/O port C. L1RSYNCB CD3ÑCarrier detect modem line for SCC3. L1RSYNCBÑReceive sync input for the serial interface TDMb. 13-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 345

    PD[6] Hi-Z Bidirectional General-Purpose I/O Port D Bit 6ÑBit 6 of the RTS4 general-purpose I/O port D. RTS4ÑActive low request to send output indicates that SCC4 is ready to transmit data. MOTOROLA Chapter 13. External Signals 13-19...

  • Page 346

    Available for MPC860 Rev. B and later only when PA9 or PA8 is not used as RXD4 or TXD4 functions. Available for MPC860 Rev. B and later. Pulled up on rev 0 to rev A.3 Hi-Z on rev 0 to rev A.3 13-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 347

    4 Disable buffer as output 5 Pull-up resistor maintains logic high state; other driver can drive signal Note: Events 1 and 4 can be in quick succession. Figure 13-4. Three-State Buffers and Active Pull-Up Buffers MOTOROLA Chapter 13. External Signals 13-21...

  • Page 348

    Typical values are on the order of 5 KW but can vary by approximately a factor of 2. 13.4 Recommended Basic Pin Connections The following sections provided recommended pin connections. 13-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 349

    Recommendations on conÞguration of the JTAG pins (including TMS, TRST, TDI, TDO, and TCK) are made in Section 38.6, ÒRecommended TAP ConÞguration.Ó TCK/DSCK or ALE_B/DSCK/AT1 (depending on the conÞguration of the DSCK function) should be connected to ground through a pull-down resistor to disable Debug MOTOROLA Chapter 13. External Signals 13-23...

  • Page 350

    The behavior of these signals is shown in Table 13-3. 13-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 351

    DSCK/AT1: high impedance IP_B[0Ð1]/IWP[0Ð1]/VFLS[0Ð1] IP_B[0Ð1]: high impedance. IWP[0Ð1]: high VFLS[0Ð1]: low IP_B3/IWP2/VF2 IP_B3: high impedance IWP2: high VF2: low IP_B4/LWP0/VF0 IP_B4: high impedance LWP0: high VF0: low IP_B5/LWP1/VF1 IP_B5: high impedance LWP1: high; VF1: low MOTOROLA Chapter 13. External Signals 13-25...

  • Page 352

    Part IV. Hardware Interface 13-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 353

    External devices can accept or provide 8, 16, and 32 bits in parallel and must follow the handshake protocol described in this section. The maximum number of bits accepted or provided during a bus transfer is deÞned as port width. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-1...

  • Page 354

    These signals are valid at the rising edge of the clock in which the transfer start signal (TS) is asserted. 14.3 Bus Interface Signal Descriptions Figure 14-2 shows the bus signals for the MPC860. 14-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 355

    Driven high indicates that a read access is in progress. Driven low indicates that a write access is in progress. Sampled by the MPC860 when an external device initiates a transaction and the memory controller was conÞgured to handle external master accesses. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-3...

  • Page 356

    Reservation/ cycle. See Section 14.4.9, ÒMemory Reservation.Ó Retry For regular transactions, the slave device drives this signal to indicate that the MPC860 must relinquish the bus and retry the cycle. 14-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 357

    Driven by the slave device to which the current transaction was addressed. Burst Inhibit Indicates that the current slave does not support burst mode. Driven by the MPC860 when the on-chip memory controller controls the slave. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-5...

  • Page 358

    The basic transfer protocol deÞnes the sequence of actions required for a complete MPC860 bus transaction. Figure 14-3 shows a simpliÞcation of the basic transfer protocol. Arbitration Address transfer Data transfer Termination Figure 14-3. Basic Transfer Protocol 14-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 359

    Asserts Bus Busy (BB) if no other master is driving Asserts Transfer Start (TS) Drives address and attributes Receives Address Returns data Asserts Transfer Acknowledge (TA) Receives data Figure 14-4. Basic Flow Diagram of a Single-Beat Read Cycle MOTOROLA Chapter 14. MPC860 External Bus Interface 14-7...

  • Page 360

    Part IV. Hardware Interface CLKOUT Receive BG and BB negated Assert BB, drive address and assert TS A[0Ð31] TSIZ[0Ð1], AT[0Ð3] BURST Data Data is Valid Figure 14-5. Single-Beat Read CycleÐBasic TimingÐZero Wait States 14-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 361

    The basic write cycle begins with a bus arbitration, followed by the address transfer, then the data transfer. The following ßow and timing diagrams show the handshakes as applicable to the Þxed transaction protocol. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-9...

  • Page 362

    Asserts Bus Busy (BB) if no other master is driving Asserts Transfer Start (TS) Drives address and attributes Drives data Asserts Transfer Acknowledge (TA) Interrupts data driving Figure 14-7. Basic Flow of a Single-Beat Write Cycle 14-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 363

    Part IV. Hardware Interface CLKOUT Receive BG and BB negated Assert BB, drive address and assert TS A[0Ð31] TSIZ[0Ð1], AT[0Ð3] BURST Data Data is sampled Figure 14-8. Basic Timing: Single-Beat Write Cycle, Zero Wait States MOTOROLA Chapter 14. MPC860 External Bus Interface 14-11...

  • Page 364

    The general case of single-beat transfers assumes that external memory has a 32-bit port size. The MPC860 provides an effective mechanism for interfacing with 16- and 8-bit port size memories by allowing transfers to these devices when they are controlled by the internal memory controller. 14-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 365

    TA after each word transferred on the data bus. The MPC860 also supports burst-inhibited transfers for slave devices that do not support bursting. For this type of cycle, the selected slave device MOTOROLA Chapter 14. MPC860 External Bus Interface 14-13...

  • Page 366

    In the case of 32-bit port size, the burst includes 4 beats. When the port size is 16 bits and controlled by the internal memory controller, the burst includes 8 beats. When the port size is 8 bits and controlled by the internal memory controller, the burst includes 16 beats. The 14-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 367

    0 ® data 1 ® data 2 ® data 3 ® data 0 ¥ Case burst of eight: data 0 ® data 1 ® data 2 ® ..® data 6 ® data 7 ® data 0 MOTOROLA Chapter 14. MPC860 External Bus Interface 14-15...

  • Page 368

    Receives Data BDIP asserted Negates Burst Data in Progress (BDIP) DonÕt drive data Returns data asserts Transfer Acknowledge (TA) Receives data BDIP asserted DonÕt drive data Figure 14-11. Basic Flow of a Burst-Read Cycle 14-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 369

    A[0Ð31], AT[0Ð3] TSIZ[0Ð1] BURST Last Beat Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Figure 14-12. Burst-Read Cycle: 32-Bit Port Size, Zero Wait State MOTOROLA Chapter 14. MPC860 External Bus Interface 14-17...

  • Page 370

    CLKOUT A[0Ð31], AT[0Ð3] TSIZ[0Ð1] BURST Last Beat Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Wait State Figure 14-13. Burst-Read CycleÐ32-Bit Port SizeÐOne Wait State 14-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 371

    TSIZ[0Ð1] BURST Last Beat Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Wait State Figure 14-14. Burst-Read CycleÐ32-Bit Port SizeÐWait States between Beats MOTOROLA Chapter 14. MPC860 External Bus Interface 14-19...

  • Page 372

    Part IV. Hardware Interface CLKOUT A[0Ð31], AT[0Ð3] TSIZ[0Ð1] BURST BDIP Data Figure 14-15. Burst-Read Cycle: One Wait State between Beats (16-Bit Port Size) 14-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 373

    Negates Burst Data in Progress (BDIP) DonÕt sample next data Asserts Transfer Acknowledge (TA) Stops driving data BDIP asserted DonÕt sample next data Figure 14-16. Basic Flow of a Burst Write Cycle MOTOROLA Chapter 14. MPC860 External Bus Interface 14-21...

  • Page 374

    Part IV. Hardware Interface CLKOUT A[0Ð31], AT[0Ð3] TSIZ[0Ð1] BURST Last beat Will drive another data BDIP Data Data is Data is Data is Data is sampled sampled sampled sampled Figure 14-17. Burst-Write CycleÐ32-Bit Port SizeÐZero Wait States 14-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 375

    ¥ Word access must have A[30Ð31] = 0b00. ¥ For burst accesses A[30Ð31] = 0b00. Misaligned accesses performed by the CPU are broken into multiple bus accesses with natural alignment. Misaligned accesses performed by external masters are not supported. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-23...

  • Page 376

    Figure 14-20 shows the device connections on the data bus. Interface Output Register D[0Ð7] D[8Ð15] D[16Ð23] D[24Ð31] 32-Bit Port Size 16-Bit Port Size 8-Bit Port Size Figure 14-20. Interface to Different Port Size Devices 14-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 377

    Each bus master must have bus request (BR), bus grant (BG), and bus busy (BB) signals. A device needing the bus asserts BR, and then waits for the arbiter to assert BG. The new MOTOROLA Chapter 14. MPC860 External Bus Interface...

  • Page 378

    The arbiter asserts BG to indicate that the bus is granted to the requesting device. BG can be negated after BR is negated or it can remain asserted to park the current master on the bus. When conÞgured for external central arbitration, BG is an input to the MPC860 from 14-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 379

    BB, regardless of how many cycles have passed since the previous master relinquished the bus. See Figure 14-22. External Bus Master MPC860 Slave 2 Figure 14-22. Masters Signals Basic Connection MOTOROLA Chapter 14. MPC860 External Bus Interface 14-27...

  • Page 380

    MPC860 grants the bus to the external device. Figure 14-24 shows the internal Þnite state machine that implements the arbiter protocol. 14-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 381

    This situation indicates that an external pull-up resistor should be connected to TS to avoid having a slave recognize this signal as asserted when no master drives it; see Figure 14-22. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-29...

  • Page 382

    These types are designated as either a normal/alternate master cycle, user/supervisor (problem/privilege), and instruction/data types. The address type signals are valid at the rising edge of the clock in which the special transfer start (STS) signal is asserted. 14-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 383

    Core-initiated, normal instruction, program trace, user mode Core-initiated, normal instruction, user mode Core-initiated, reservation data, user mode Core-initiated, normal data, user mode DMA-initiated, normal, AT[1Ð3] user-programmable (see IDMA and DMA function code registers) MOTOROLA Chapter 14. MPC860 External Bus Interface 14-31...

  • Page 384

    (PTR and RSV), if desired. ¥ PTR is low when the following is true: Ñ AT0 = 0 (CPU access) Ñ AT2 = 0 (Instruction) Ñ AT3 = 0 (Program Trace) 14-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 385

    See Figure 14-25 and Figure 14-26. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-33...

  • Page 386

    The protocol tries to optimize reservation cancellation such that a PowerPC processor is notiÞed of memory reservation loss on a remote bus only when it has issued a STWCX cycle to that address. 14-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 387

    ¥ Holds one reservation for each local master capable of memory reservations. ¥ Sets the reservation when that master issues a load and reserve request. ¥ Clears the reservation when another master issues a store to the reservation address. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-35...

  • Page 388

    The advantage of KR is that it is cheaper and easier to implement. Figure 14-28 shows the reservation protocol for a multi-level (local) bus. The system describes a situation in which the reserved location is in the remote bus. 14-36 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 389

    To properly control termination of a bus cycle for a bus error, TEA must be asserted at the same time or before TA is asserted. TEA should be negated MOTOROLA Chapter 14. MPC860 External Bus Interface...

  • Page 390

    BR and BB are negated together. Normal arbitration resumes one clock cycle later. CLKOUT BG (Output) Allow external master to gain the bus A[0Ð31] TSIZ[0Ð1] BURST Data RETRY Figure 14-29. Retry Transfer TimingÐInternal Arbiter 14-38 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 391

    When RETRY is asserted as a termination signal on the second or third data beat of the access (being the Þrst data beat acknowledged by a normal TA assertion), it is processed by the MPC860 as a TEA. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-39...

  • Page 392

    MPC860 to complete the access process the RETRY assertion as a TEA. Table 14-6 summarizes how the MPC860 recognizes the termination signals provided by the slave device that is addressed by the initiated transfer. 14-40 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 393

    Part IV. Hardware Interface Table 14-6. Termination Signals Protocol RETRY/KR Action Asserted Transfer error termination Negated Asserted Normal transfer termination Negated Negated Asserted Retry transfer termination/kill reservation MOTOROLA Chapter 14. MPC860 External Bus Interface 14-41...

  • Page 394

    Part IV. Hardware Interface 14-42 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 395

    ¥ Clock dividers are provided for low-power modes and internal clocks ¥ Contains Þve major power-saving modes Ñ Normal (high and low) Ñ Doze (high and low) Ñ Sleep Ñ Deep sleep Ñ Power down MOTOROLA Chapter 15. Clocks and Power Control 15-1...

  • Page 396

    (¸4 or ¸16) dividers Clock brgclk Drivers syncclk CLKOUT CLKOUT Driver tmbclk tbclk TMBclk Driver rtdiv rtsel ¸4 RTC /PIT Clock pitrtclk and DRIVER XTAL CRYSTAL EXTAL ¸512 Oscillator (OSCM) Figure 15-1. Clock Source and Distribution 15-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 397

    EXTCLK. This is because noise from the EXTCLK clock source will couple into the crystal oscillator circuit, and will in many cases not allow the system phase-locked loop (SPLL) to lock. The converse, however, is allowable; EXTCLK MOTOROLA Chapter 15. Clocks and Power Control 15-3...

  • Page 398

    Motorola reserves the right to perform these changes, and designers should be prepared to modify their crystal circuits appropriately should these changes cause their crystal circuit 15-4 MPC860 PowerQUICC UserÕs Manual...

  • Page 399

    Second, the programmability of the oscillator enables the system to operate at a variety of frequencies with only a single external clock source. The MPC860 SPLL block diagram is shown in Figure 15-4. MOTOROLA Chapter 15. Clocks and Power Control 15-5...

  • Page 400

    MODCK[1-2] pins. The SPLL immediately begins to use the multiplication factor PLPRCR[MF] value and external clock source for OSCCLK determined by the sampled MODCK[1-2] pin and attempts to achieve lock; therefore, the MODCK[1-2] signals should 15-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 401

    For input frequencies greater than 15 MHz and (MF+1)£2, this jitter is less than ±0.6ns. Otherwise, this jitter is not guaranteed. However, for (MF+1)<10 and input frequencies greater than 10 MHz, this jitter is less than ±2ns. MOTOROLA Chapter 15. Clocks and Power Control 15-7...

  • Page 402

    If there is no overlap between two ranges of operation, choose the minimum or maximum value of the recommended XFC range for the normal operating frequency of the system, whichever is nearest the range for the other frequency. 15-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 403

    The MPC860 uses the following 9 internal clock signals, which are derived from the SPLL output clock (VCOOUT): ¥ General system clocksÑGCLK1C, GCLK2C, GCLK1, GCLK2 ¥ Memory controller and external bus clocksÑGCLK1_50, GCLK2_50 ¥ Baud rate generator clockÑBRGCLK ¥ Synchronization clocksÑSYNCCLK, SYNCCLKS MOTOROLA Chapter 15. Clocks and Power Control 15-9...

  • Page 404

    CPM. They are not active when the MPC860 is in sleep or deep-sleep modes. GCLKx can be dynamically switched between two different frequencies determined by dividers programmed in SCCR[DFNH] and SCCR[DFNL], as shown in Figure 15-6. 15-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 405

    The external bus clocks GCLK1_50 and GCLK2_50 are derived from GCLK1 and GCLK2, as determined by the SCCR[EBDF]. SCCR[EBDF] is cleared by HRESET, and thus GCLK1_50 and GCLK2_50 default to GCLK1 and GCLK2. The MOTOROLA Chapter 15. Clocks and Power Control 15-11...

  • Page 406

    The low-power frequency dividers described in Section 15.3.1.1, ÒThe Internal General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2)Ó also effect the frequency and duty cycle of GCLK1_50, GCLK2_50, and CLKOUT. For an example of this, see Figure 15-9. 15-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 407

    CLKOUT reduces power consumption, noise, and electromagnetic interference on the printed circuit board. While the SPLL is acquiring lock, the CLKOUT signal does not oscillate and remains in a low state. MOTOROLA Chapter 15. Clocks and Power Control 15-13...

  • Page 408

    SYNCCLK) are used by the signal synchronization circuitry in the serial ports of the communication processor module. The signal synchronization circuitry is used to sample and synchronize asynchronous external signals provided to these ports. SYNCCLK allows 15-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 409

    32.768 KHz or 38.4 KHz crystal with the OSCM be used for the PITRTCLK source if the RTC is to be used. MOTOROLA Chapter 15. Clocks and Power Control 15-15...

  • Page 410

    The various modules of the MPC860 are connected to four distinct power rails. These power rails have different requirements, as explained in the following sections. The organization of the power rails is shown in Figure 15-12. 15-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 411

    RTC, PIT, TB, and DEC 15.4.1 I/O Buffer Power (VDDH) The I/O buffers, logic, and clock control are fed by a 3.3V power supply. VDDH must in all cases be greater than or equal to VDDL. MOTOROLA Chapter 15. Clocks and Power Control 15-17...

  • Page 412

    When the CPM is idle, it uses its own power-saving mechanism to shut down automatically. Low-power modes are controlled in the PLPRCR[LPM] and PLPRCR[CSRC]. Events can cause automatic changes from one low-power mode to another. These events include 15-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 413

    32 KHz ~10mA, LPM=11 from RTC, + power supply KAPWR = 3.0V TEXPS=0 PIT, DEC, wake-up Temperature = 50° C TB followed (PwSp_Wake+ 16 by external ms at 32 KHz) hard reset MOTOROLA Chapter 15. Clocks and Power Control 15-19...

  • Page 414

    Software is active only in normal high/low modes. Software initiation of power-down mode requires that the TEXP output be used by external logic to gate main power (VDDH, VDDL, and VDDSYN). MPC860 Figure 15-13. Low-Power Mode Flowchart 15-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 415

    GCLKxC clocks to the core, MMUs, and caches are disabled. However, the CPM and SIU continue to function as normal. Doze high mode selected PLPRCR[CSRC]=0, MSR[POW]=1, PLPRCR[LPM]=01. In doze high mode, the GCLKx frequency is determined by MOTOROLA Chapter 15. Clocks and Power Control 15-21...

  • Page 416

    SCCR[PRQEN] is set; otherwise it will enter normal low mode. Upon resumption of processing in normal high or low mode, the MPC860 will jump to the external interrupt vector to process the interrupt source. When the core returns from the 15-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 417

    500 OSCCLK clocks (if OSCCLK is sourced by OSCM) or a maximum of 1000 clocks (if OSCCLK is sourced by EXTCLK). Deep-sleep mode is selected if PLPRCR[LPM]=11 and PLPRCR[TEXPS]=1. Note also that PLPRCR[TMIST] should be cleared before entering deep-sleep mode; for more MOTOROLA Chapter 15. Clocks and Power Control 15-23...

  • Page 418

    Figure 15-14. The MPC860 should then go through a normal hardware reset sequence. When performing this hardware reset sequence, it is important to allow enough time for the oscillator to warm up and the SPLL to lock. 15-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 419

    (RTC) if a power shutdown or power failure should occur. The backup KAPWR source is used to maintain the RTC. In this conÞguration, no provision is made for automatic wake-up from power-down mode. Instead, it is assumed that the appropriate reset MOTOROLA Chapter 15. Clocks and Power Control 15-25...

  • Page 420

    (when software clears PLPRCR[TMIST]). Note, however, this requires that PLPRCR[TMIST] must be cleared before entry into any low-power mode other than normal high mode. 15-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 421

    The COM Þeld is cleared by hard reset. 00 =Clock output enabled full-strength buffer. 01 =Clock output enabled half-strength output buffer. 10 =Reserved. 11 =Clock output disabled. 3Ð5 Ñ Reserved, should be cleared. MOTOROLA Chapter 15. Clocks and Power Control 15-27...

  • Page 422

    BRGCLK signal. Changing the value of this Þeld does not result in a loss-of-lock condition. This Þeld is cleared by a power-on or hard reset. 00 = Divide by 1 (normal operation). 01 = Divide by 4. 10 = Divide by 16. 11 = Divide by 64. 15-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 423

    15.6.2 PLL, Low-Power, and Reset Control Register (PLPRCR) The 32-bit system PLL, low-power, and reset control register (PLPRCR) is powered by a keep-alive power supply and is used to control the system frequency and low-power mode operation. MOTOROLA Chapter 15. Clocks and Power Control 15-29...

  • Page 424

    When TEXPS is set, the TEXP external signal is asserted and when it is reset, the TEXP external signal is negated. 0 = TEXP is negated. 1 = TEXP is asserted. Ñ Reserved, should be cleared. 15-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 425

    Table 15-10 describes PLPRCR[CSR] and DER[CHSTPE] bit combinations. Table 15-10. PLPRCR[CSR] and DER[CHSTPE] Bit Combinations PLPRCR[CSR] DER[CHSTPE] Checkstop Mode Result Ñ Ñ Ñ Enter debug mode Ñ Automatic reset Ñ Enter debug mode MOTOROLA Chapter 15. Clocks and Power Control 15-31...

  • Page 426

    Part IV. Hardware Interface 15-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 427

    The following is a list of the memory controllerÕs main features: ¥ Eight memory banks Ñ 32-bit address decode with mask Ñ Variable block sizes (32 Kbytes to 4 Gbytes) Ñ Byte parity generation/checking MOTOROLA Chapter 16. Memory Controller 16-1...

  • Page 428

    Ñ Internal address multiplexing for all on-chip bus masters supporting 64-, 128-, 256-, and 512-Kbyte, and 1-, 2-, 4-, 8-, 16-, 32-, 64-, 128-, 256-Mbyte page banks Ñ Glueless interface to EDO, self refresh, and synchronous DRAM devices 16-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 429

    Memory Command Register (MCR) Memory Data Register (MDR) Parity Error Memory Status Register (MSTAT) DP[0Ð3] Memory Address Register (MAR) Parity DP[0Ð31] Logic Memory Periodic Timer Prescale Register (MPTPR) Figure 16-1. Memory Controller Block Diagram MOTOROLA Chapter 16. Memory Controller 16-3...

  • Page 430

    (DP[0Ð3]), one for each data byte lane on the MPC860 system bus. The parity on the bus is checked only if the memory bank accessed in the current transaction has parity enabled. Parity checking/generation can be enabled for a 16-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 431

    The UPM speciÞes a set of signal patterns for a user-speciÞed number of clock cycles. The UPM RAM pattern run by the memory controller is selected according to the type of external access transacted. At every clock cycle, the logical value of the external MOTOROLA Chapter 16. Memory Controller 16-5...

  • Page 432

    Ö Memory command register (MCR) Ö Machine A mode register (MAMR) Ö Machine B mode register (MBMR) Ö Memory data register (MDR) Ö Memory address register (MAR) Ö Memory periodic timer prescaler register (MPTPR) 16-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 433

    Table 16-2. Access Granularities for Predefined Port Sizes Bytes Half Words PredeÞned Words (on Word Port Size Boundaries) Even Even Ö Ö 8-bit Ñ Ñ Ñ Ö Ö Ö (on D[0Ð15]) 16-bit Ñ Ñ Ö Ö Ö Ö Ö 32-bit MOTOROLA Chapter 16. Memory Controller 16-7...

  • Page 434

    The base registers (BR0ÐBR7) contain the base address and address types that the memory controller uses to compare the value on the address bus with the current address accessed. It also includes a memory attribute and selects the machine for memory operation handling. 16-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 435

    Addr (IMMR & FFFF0000) + 0x100 Field PARE Ñ Reset 00_000 Addr (IMMR & FFFF0000) + 0x102 This value depends on the value of the hard reset conÞguration word. Figure 16-6. BR0 Reset Defaults MOTOROLA Chapter 16. Memory Controller 16-9...

  • Page 436

    1 This bank is valid. The CS signal does not assert until V is set. 16.4.2 Option Registers (ORx) The option registers (OR0ÐOR7), shown in Figure 16-7, contain the address and address type mask bit for address bus comparison. It also includes all GPCM parameters. 16-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 437

    17 18 19 24 25 26 27 Field CSNT/SAM ACS/G5LA,G5LS BIH SETA TRLX EHTR Ñ Reset 1111 OR0: R; R/W for all others Addr (IMMR & FFFF0000) + 0x106 Figure 16-8. OR0 Reset Defaults MOTOROLA Chapter 16. Memory Controller 16-11...

  • Page 438

    0 Internal or external transfer acknowledge can acknowledge this access, whichever comes Þrst. 1 The memory controller does not generate TA for this bank; instead the peripheral must generate it on the external TA signal. 16-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 439

    Ñ Reserved, should be cleared. 16.4.4 Machine A Mode Register/ achine B Mode Registers (MxMR) The machine x mode register (MAMR and MBMR) contain the conÞguration for UPMA and UPMB, respectively. See Figure 16-1. MOTOROLA Chapter 16. Memory Controller 16-13...

  • Page 440

    The maximum disable period is four clock cycles. If more than 4 cycles are required, they must be added explicitly in the UPM RAM words. 00 1-cycle disable period 01 2-cycle disable period 10 3-cycle disable period 11 4-cycle disable period Ñ Reserved, should be cleared. 16-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 441

    UPM pattern to initialize SDRAM. Field Ñ Ñ Reset 0000_0000_0000_0000 Addr (IMMR & FFFF0000) + 0x168 Field Ñ MCLF Ñ Reset 0000_0000_0000_0000 Addr (IMMR & FFFF0000) + 0x16A Figure 16-11. Memory Command Register (MCR) MOTOROLA Chapter 16. Memory Controller 16-15...

  • Page 442

    MDR must be set up before issuing a write command to READ WRITE the MCR. Field Reset 0000_0000_0000_0000 Address (IMMR & FFFF0000) + 0x17C Field Reset 0000_0000_0000_0000 Address (IMMR & FFFF0000) + 0x17E Figure 16-12. Memory Data Register (MDR) 16-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 443

    See Section 15.3, ÒClock Signals.Ó Field Ñ Reset 0000_001x 0000_0000 Addr (IMMR & FFFF0000) + 0x17A Figure 16-14. Memory Periodic Timer Prescaler Register (MPTPR) MOTOROLA Chapter 16. Memory Controller 16-17...

  • Page 444

    If BRx[MS] selects the GPCM, the attributes for the memory cycle are taken from ORx. These attributes include the CSNT, ACS[0Ð1], SCY[0Ð3], TRLX, EHTR, and SETA Þelds. See Table 16-11 for signal behavior and system response. 16-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 445

    Figure 16-16 shows a basic connection between the MPC860 and an external peripheral device. Here, CS (the strobe output for the memory access) is connected directly to CE of the memory device and R/W is connected to the respective R/W in the peripheral device. 16-19 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 446

    Here, CS is connected directly to CE of the memory device. The WE signals are connected to the respective W signal in the memory device where each WE corresponds to a different data byte. 16-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 447

    Figure 16-20. Clock Address CSNT = 1 Data Figure 16-19. GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0) MOTOROLA Chapter 16. Memory Controller 16-21...

  • Page 448

    MPC860 memory controller. See Figure 16-21 and Figure 16-22. Clock Address ACS = 10 ACS = 11 Data Figure 16-21. GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, and TRLX = 1) 16-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 449

    (SETA and TRLX = 1), the memory controller does not support external devices that provide TA to complete the transfer with zero wait states. The minimum access duration in this case is 3 clock cycles. MOTOROLA Chapter 16. Memory Controller 16-23...

  • Page 450

    Figure 16-23 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 1, TRLX =1) Clock Address Data Figure 16-24. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX =1) 16-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 451

    See Figure 16-25 through Figure 16-28 for details. Clock Address Data Hold Time Figure 16-25. GPCM Read Followed by Write (EHTR = 0) MOTOROLA Chapter 16. Memory Controller 16-25...

  • Page 452

    Long hold time allowed Figure 16-26. GPCM Write Followed by Read (EHTR = 1) Clock Address Data Hold Time Long hold time allowed Figure 16-27. GPCM Read Followed by Read from Different Banks (EHTR = 1) 16-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 453

    BR0. After the Þrst write to OR0, the boot chip-select can only be restarted on hardware reset. The initial values of the boot bank in the memory controller are described in Table 16-12. MOTOROLA Chapter 16. Memory Controller 16-27...

  • Page 454

    Figure 16-30 shows the timing for TRLX = 0 when an external asynchronous master accesses SRAM. TA, WE, and OE remain asserted until the external master negates AS, at which point they deassert asynchronously. 16-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 455

    During a burst cycle, the user sees the chip-select assertion follow the same pattern as for a single-beat cycle. However, BI remains negated, and the burst continues for the following data beats after the negation of chip-select following TA for the Þrst data beat. MOTOROLA Chapter 16. Memory Controller 16-29...

  • Page 456

    RAM word from the RAM array to drive the general-purpose lines, byte-selects, and chip-selects. If the UPM reads a RAM word with WAEN set, the external UPWAIT signal is sampled and synchronized by the memory controller and the current request is frozen. 16-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 457

    BRx. The value in BRx[MS] selects the UPM to handle the memory access. The user must ensure that the UPM is appropriately initialized before a request. MOTOROLA Chapter 16. Memory Controller 16-31...

  • Page 458

    TEA, SRESET, or HRESET. The UPM provides a mechanism by which memory control signals can meet the timing requirements of the device without losing data. The mechanism is the exception pattern which deÞnes how the UPM deasserts its signals in a controlled manner. 16-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 459

    In Figure 16-35, if SCCR[EBDF] = 01, CLKOUT equals the system clock divided by 2. In this scheme GCLK1_50 does not have a 50% duty cycle. System Clock CLKOUT GCLK1_50 GCLK2_50 Clock Phase Figure 16-35. UPM Clock Scheme Two (Division Factor = 2) MOTOROLA Chapter 16. Memory Controller 16-33...

  • Page 460

    GPL1 G1T4 G1T3 G1T4 G1T4 G1T3 GPL2 G2T4 G2T3 G2T4 G1T4 G2T3 Clock Phase RAM Word 1 RAM Word 2 Figure 16-36. UPM Signals Timing Example One (Division Factor = 1, EBDF = 00) 16-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 461

    RAM Array Words Deep GCLK2_50 Signals Timing Generator CS Signal BS Signal Selected Bank TSIZ, PS, A[30Ð31] Selector Selector CS[0Ð7] GPL0 GPL1 GPL2 GPL3 GPL4 GPL5 BS[0Ð3] Figure 16-38. RAM Array and Signal Generation MOTOROLA Chapter 16. Memory Controller 16-35...

  • Page 462

    1 Negated at the rising edge of GCLK1_50. The Þnal value of the BS lines depends on the values of BRx[PS], the TSIZ lines, and A[30Ð31] for the access. See Section 16.6.4.3, ÒByte-Select Signals (BxTx).Ó 16-36 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 463

    0 The data bus should be sampled at the rising edge of GCLK2_50 for a read in this cycle. 1 The data bus should be sampled at the falling edge of GCLK2_50 for a read in this cycle. MOTOROLA Chapter 16. Memory Controller...

  • Page 464

    TA is output at the rising edge of GCLK2_50. 0 TA is driven low on the rising edge of GCLK2_50. The bus master samples it low in the next clock cycle. 1 TA is driven high on the rising edge of GCLK2_50. 16-38 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 465

    BSTx bit and the values of BRx[PS], TSIZn, and A[30Ð31] in the current cycle.The BS signals are also controlled by the port size of the accessed bank, the transfer size of the transaction, and the address accessed. Figure 16-41 shows how UPMs control BS signals. MOTOROLA Chapter 16. Memory Controller 16-39...

  • Page 466

    G5LS, as shown in Figure 16-42. This allows it to assert earlier (simultaneous with TS, for an internal master), which can speed up the memory interface, particularly when GPL5 is used as a control signal for external address multiplexers. 16-40 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 467

    UPM cycle. GPL_A5 is driven low at the falling edge of GCLK1_50 in the current UPM cycle. GPL_A5 is driven high at the falling edge of GCLK1_50 in the current UPM cycle. MOTOROLA Chapter 16. Memory Controller 16-41...

  • Page 468

    Continued loop execution depends on the loop counter. If the counter is not zero, the next RAM word executed is the loop start word. Otherwise, the next RAM word executed is the one after the loop end word. Loops can be executed sequentially but cannot be nested. 16-42 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 469

    RAM word, as shown in Figure 16-43. The AMX Þeld can be used to output the contents of MAR on the address signals. Figure 16-43 shows address multiplex timing. MOTOROLA Chapter 16. Memory Controller 16-43...

  • Page 470

    A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Address Multiplexing A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 is Enabled Ñ A10 A11 A12 A13 A14 A15 A16 A17 A18 16-44 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 471

    A20ÐA31 16 Mbyte A19ÐA31 32 Mbyte A18ÐA31 64 Mbyte A17ÐA31 16 Mbyte A20ÐA31 32 Mbyte A19ÐA31 64 Mbyte A18ÐA31 128 Mbyte A17ÐA31 256 Mbyte A16ÐA31 64 Mbyte A19ÐA31 128 Mbyte A18ÐA31 256 Mbyte A17ÐA31 MOTOROLA Chapter 16. Memory Controller 16-45...

  • Page 472

    A17ÐA30 64 Mbyte A16ÐA30 8 Mbyte A20ÐA30 16 Mbyte A19ÐA30 32 Mbyte A18ÐA30 64 Mbyte A17ÐA30 32 Mbyte A19ÐA30 64 Mbyte A18ÐA30 128 Mbyte A17ÐA30 256 Mbyte A16ÐA30 128 Mbyte A18ÐA30 256 Mbyte A17ÐA30 16-46 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 473

    1/2 clock early, which can be useful during burst reads. This feature should be used only in systems without external synchronous bus devices. MOTOROLA Chapter 16. Memory Controller 16-47...

  • Page 474

    If the WAEN bit is set and UPWAIT was sampled high on the previous falling edge of GCLK2_50, the logical value of the external signals are frozen to the value deÞned at the 16-48 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 475

    AS should deassert (similar to DTACK in the 68000 bus). The wait state is exited when AS is negated, at which point all external signals controlled by the UPM are driven high asynchronously from the AS deassertion. External signals are MOTOROLA Chapter 16. Memory Controller 16-49...

  • Page 476

    MAMR[GPLA4DIS] and MBMR[GPLB4DIS] enable this mechanism. ¥ The external TA mechanism is used only in accesses controlled by the GPCM. ORx[SETA] speciÞes whether TA is generated internally or externally. The following examples show how the two mechanisms work. 16-50 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 477

    Synchronous masters initiate a transfer by asserting TS. A[0Ð31], RD/WR, BURST, and TSIZ must be stable before the rising edge of CLKOUT after TS is asserted and until the last TA is negated. Because the external master operates synchronously with the MPC860, MOTOROLA Chapter 16. Memory Controller 16-51...

  • Page 478

    A wait mechanism in the UPM supports handshaking for external asynchronous masters. This is provided with an AS input signal and the WAEN bit in the UPM RAM words. See Section 16.6.4.11, ÒThe Wait Mechanism (WAEN).Ó 16-52 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 479

    Asynchronous external masters behave as described in Section 16.5.3, ÒExternal Asynchronous Master Support.Ó CLKOUT A[6Ð27] A[28Ð31] BURST TSIZ Data Address Memory Match and Device Compare Access Figure 16-47. Synchronous External Master Access MOTOROLA Chapter 16. Memory Controller 16-53...

  • Page 480

    ORx[G5LS]. In this example, the accessed critical word is addressed at BADDR[28Ð29] = 10, which then increments and wraps around to the word before the critical word (01) for subsequent beats of this burst access. 16-54 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 481

    Part IV. Hardware Interface DRAM BS[0Ð3] Bank GPL_A5 Multiplexer BADDR[28Ð30] A[6Ð31] D[0Ð31] BURST External MPC860 Master TSIZ[0Ð1] Figure 16-49. Synchronous External Master Interconnect Example MOTOROLA Chapter 16. Memory Controller 16-55...

  • Page 482

    Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 Figure 16-50. Synchronous External Master: Burst Read Access to Page Mode DRAM 16-56 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 483

    The state of GPL_A5 in the Þrst clock cycle of the memory device access is determined by the value of the corresponding ORx[G5LS]. DRAM BS[0Ð3] GPL_A5 Multiplexer A[6Ð31] D[0Ð31] External Master TSIZ[0Ð1] MPC860 Arbitration Signals External Arbiter Figure 16-51. Asynchronous External Master Interconnect Example MOTOROLA Chapter 16. Memory Controller 16-57...

  • Page 484

    16.9 Memory System Interface Examples The following examples show how to connect and set up the UPM RAM array for two types of DRAMÑpage mode DRAM and page mode extended data-out DRAM. The values used 16-58 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 485

    RAM array. A blank cell in the Þgures indicates a donÕt care bit, which is typically programmed to logic 1 to conserve power. MOTOROLA Chapter 16. Memory Controller 16-59...

  • Page 486

    Selects two disable timer clock cycles GPLA4DIS Disables the UPWAITA signal RLFA 0011 Selects three loop iterations for read WLFA 0011 Selects three loop iterations for write Selects column address on Þrst cycle Supports burst accesses 16-60 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 487

    Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 Figure 16-54. Single-Beat Read Access to Page-Mode DRAM MOTOROLA Chapter 16. Memory Controller 16-61...

  • Page 488

    Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS WSS+1 WSS+2 Figure 16-55. Single-Beat Write Access to Page Mode DRAM 16-62 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 489

    Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 Figure 16-56. Burst Read Access to Page-Mode DRAM (No LOOP) MOTOROLA Chapter 16. Memory Controller 16-63...

  • Page 490

    Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 Figure 16-57. Burst Read Access to Page-Mode DRAM (LOOP) 16-64 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 491

    Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 Figure 16-58. Burst Write Access to Page-Mode DRAM (No LOOP) MOTOROLA Chapter 16. Memory Controller 16-65...

  • Page 492

    Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS WBS+1 WBS+2 WBS+3 WBS+4 Figure 16-59. Burst Write Access to Page-Mode DRAM (LOOP) 16-66 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 493

    Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 Figure 16-60. Refresh Cycle (CAS before RAS) to Page-Mode DRAM MOTOROLA Chapter 16. Memory Controller 16-67...

  • Page 494

    DRAM access time. For a 16-bit port size memory, the reduction is from 17 to 10 cycles and when an 8-bit port size memory is connected, the reduction is from 33 to 18 cycles. 16-68 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 495

    Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 Figure 16-62. Optimized DRAM Burst Read Access MOTOROLA Chapter 16. Memory Controller 16-69...

  • Page 496

    Þgures show the RAM array contents that handle each of the possible cycles; each column represents a different word in the RAM array. A blank cell indicates a donÕt care bit (typically programmed to logic 1 to conserve power). 16-70 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 497

    Selects two disable timer clock cycles GPLB4DIS MBMR Disables the UPWAITB signal RLFB MBMR 0011 Selects three loop iterations for read WLFB MBMR 0011 Selects three loop iterations for write Selects column address on Þrst cycle Supports burst accesses MOTOROLA Chapter 16. Memory Controller 16-71...

  • Page 498

    Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 RSS+3 RSS+4 Figure 16-64. EDO DRAM Single-Beat Read Access 16-72 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 499

    Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS WSS+1 WSS+2 WSS+3 Figure 16-65. EDO DRAM Single-Beat Write Access MOTOROLA Chapter 16. Memory Controller 16-73...

  • Page 500

    Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 RBS+9 RBS+10 Figure 16-66. EDO DRAM Burst Read Access 16-74 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 501

    Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 WBS+9 Figure 16-67. EDO DRAM Burst Write Access MOTOROLA Chapter 16. Memory Controller 16-75...

  • Page 502

    Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 PTS+3 PTS+4 Figure 16-68. EDO DRAM Refresh Cycle (CAS before RAS) 16-76 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 503

    Ð Bit 22 Ð Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 Figure 16-69. EDO DRAM Exception Cycle MOTOROLA Chapter 16. Memory Controller 16-77...

  • Page 504

    Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 xxS+1 xxS+2 xxS+3 xxS+4 xxS+5 xxS+6 xxS+7 xxS+8 xxS+9 xxS+10 Figure 16-70. Blank Work Sheet for a UPM 16-78 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 505

    Signals shared among all sockets consist of the address and data buses, socket control signals, and synchronous socket status signals. A[6Ð31] and D[0Ð15] are the address and data signals of the system bus. Figure 17-1 shows the PCMCIA host adapter moduleÕs external signals. MOTOROLA Chapter 17. PCMCIA Interface 17-1...

  • Page 506

    (IORD),(IOWR) (IORD_A),(IOWR_A) RESET_A/B buffer with OE POE_A/B Transparent latch with OE Address_A[25:0] A[6:31] REG_A ALE_A/B Vcc_A WAIT_A/B, IOIS16_A/B RDY/BSY_x, BVD1_x,BVD2_x Chip Vdd CD1_x, CD2_x, VS1_x, VS2_x SPKROUT Figure 17-1. System with Two PCMCIA Sockets 17-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

  • Page 507

    Write enable/program. Output. During PCMCIA accesses, WE_x is used to latch memory write data to the PC card in a PCMCIA socket. Can also be used as the programming strobe for PC cards using programmable memory technologies. MOTOROLA Chapter 17. PCMCIA Interface 17-3...

  • Page 508

    STSCHG and is generated by I/O PC cards. STSCHG must be held negated when the Òsignal on changeÓ bit and ÒchangedÓ bit in the card status register on the PC card are either or both zero. STSCHG must be asserted when both bits = 1. 17-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...