Features - Motorola MPC860 PowerQUICC User Manual

Part II. PowerPC Microprocessor Module

4.2 Features

Figure 4-1 shows the basic features of the MPC860.
Completion
Queue
CQ5
CQ4
CQ3
CQ2
CQ1
CQ0
One Instruction Retired
per Clock
Additional Features
¥ Power Dissipation Control
¥ Time Base Counter
¥ Decrementer
¥ JTAG
¥ BDM interface
¥ Clock Multiplier
4-4
Sequential
Fetcher
32-Bit
Instruction
Queue
IQ3
IQ2
IQ1
IQ0
32-Bit (One Instruction)
32-Bit
Integer
Unit
+
Ú
*
XER
ALU
Performs
EA
Calculation
Data
MMU
32 Kbyte
DTLB
Tags
U-Bus Interface
Figure 4-1. Block Diagram of the Core
MPC860 PowerQUICC UserÕs Manual
32-Bit (One Instruction)
32-Bit
Branch
Processing Unit
CTR
CR
LR
INSTRUCTION UNIT
32-Bit
GPR File
(32-Entry)
L-Bus
¥ ¥
¥
32-Bit
32-Bit
4 Kbyte
Tags
D-Cache
Load/Store
Unit (LSU)
Instruction
MMU
32 Kbyte
ITLB
4 Kbyte
I-Cache
MOTOROLA