Motorola MPC860 PowerQUICC User Manual page 339

Name Reset
IP_B5 Hi-Z
LWP1
VF1
IP_B6 Hi-Z
DSDI
AT0
IP_B7 Hi-Z
PTR
AT3
OP[0Ð1] Low
OP2 Hi-Z
MODCK1
STS
OP3 Hi-Z
MODCK2
DSDO
MOTOROLA
Table 13-1. Signal Descriptions (Continued)
Number Type
J4 Bidirectional Input Port B 5ÑThe MPC860 monitors this input; its value and
K3 Bidirectional
Three-state
H1 Bidirectional
Three-state
L4, L2 Output
L1 Bidirectional Output Port 2ÑThis output is generated by the MPC860 as a
M4 Bidirectional Output Port 3ÑThis output is generated by the MPC860 as a
Chapter 13. External Signals
Description
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Load/Store Watchpoint 1ÑThis output reports the detection of
a data watchpoint in the program ßow executed by the core.
Visible Instruction Queue Flushes StatusÑThe MPC860
outputs VF1 with VF0 and VF2 when instruction ßow tracking is
required. VFn reports the number of instructions ßushed from
the instruction queue in the core.
Input Port B 6ÑThe MPC860 senses this input and its value
and changes are reported in the PIPR and PSCR of the
PCMCIA interface. See Chapter 17, ÒPCMCIA Interface.Ó
Development Serial Data InputÑData input for the debug port
interface. See Chapter 37, ÒSystem Development and
Debugging.Ó
Address Type 0ÑThe MPC860 drives this bidirectional
three-state line when it initiates a transaction on the external
bus. If high (1), the transaction is the CPM. If low (0), the
transaction initiator is the CPU. This signal is not used for
transactions initiated by external masters.
Input Port B 7ÑThe MPC860 monitors this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Program TraceÑTo allow program ßow tracking, the MPC860
asserts this output to indicate an instruction fetch is taking
place.
Address Type 3ÑThe MPC860 drives the bidirectional
three-state signal when it starts a transaction on the external
bus. When the core initiates a transfer, AT3 indicates whether it
is a reservation for a data transfer or a program trace
indication for an instruction fetch. This signal is not used for
transactions initiated by external masters.
Output Port 0Ð1ÑThe MPC860 generates these outputs as a
result of a write to the PGCRA register in the PCMCIA
interface.
result of a write to the PGCRB register in the PCMCIA
interface.
Mode Clock 1ÑInput sampled when PORESET is negated to
conÞgure PLL/clock mode.
Special Transfer StartÑThe MPC860 drives this output to
indicate the start of an external bus transfer or of an internal
transaction in show-cycle mode.
result of a write to the PGCRB register in the PCMCIA
interface.
Mode Clock 2ÑThis input is sampled at the PORESET
negation to conÞgure the PLL/clock mode of operation.
Development Serial Data OutputÑOutput data from the debug
port interface.
Part IV. Hardware Interface
13-13