Motorola MPC860 PowerQUICC User Manual page 104

Part I. Overview
Name Type
DP3 Bidirectional
IRQ6 Three-state
BR Bidirectional Bus RequestÑThis signal is asserted low when a possible master is requesting
BG Bidirectional Bus GrantÑThis signal is asserted low when the arbiter of the external bus grants
BB Bidirectional
Active Pull-up
FRZ Bidirectional FreezeÑOutput asserted to indicate that the core is in debug mode.
IRQ6
IRQ0 Input
IRQ1 Input
IRQ7 Input
CS[0Ð5] Output
CS6 Output
CE1_B
CS7 Output
CE2_B
3-6
Table 3-1. Signal Descriptions (Continued)
Data Parity 3ÑThis line provides parity generation and checking for D[24Ð31] for
transfers to a slave device initiated by the MPC860. The parity function can be
deÞned independently for each one of the addressed memory banks (if controlled by
the memory controller) and for the rest of the slaves on the external bus. Parity
generation and checking is not supported for external masters.
Interrupt Request 6ÑOne of eight external inputs that can request (by means of the
internal interrupt controller) a service routine from the core. Note that the interrupt
request signal sent to the interrupt controller is the logical AND of this line (if deÞned
as IRQ6) and the FRZ/IRQ6 (if deÞned as IRQ6).
ownership of the bus. When the MPC860 is conÞgured to work with the internal
arbiter, this signal is conÞgured as an input. When the MPC860 is conÞgured to work
with an external arbiter, this signal is conÞgured as an output and asserted every
time a new transaction is intended to be initiated (no parking on the bus).
the bus to a speciÞc device. When the MPC860 is conÞgured to work with the
internal arbiter, BG is conÞgured as an output and asserted every time the external
master asserts BR and its priority request is higher than any internal sources
requiring a bus transfer. However, when the MPC860 is conÞgured to work with an
external arbiter, BG is an input.
Bus BusyÑThis signal is asserted low by a master to show that it owns the bus. The
MPC860 asserts BB after the arbiter grants it bus ownership and BB is negated.
Interrupt Request 6ÑOne of eight external inputs that can request (by means of the
internal interrupt controller) a service routine from the core. Note that the interrupt
request signal sent to the interrupt controller is the logical AND of FRZ/IRQ6 (if
deÞned as IRQ6) and DP3/IRQ6 (if deÞned as IRQ6).
Interrupt Request 0ÑOne of eight external inputs that can request (by means of the
internal interrupt controller) a service routine from the core.
Interrupt Request 1ÑOne of eight external inputs that can request (by means of the
internal interrupt controller) a service routine from the core.
Interrupt Request 7ÑOne of eight external inputs that can request (by means of the
internal interrupt controller) a service routine from the core.
Chip SelectÑThese outputs enable peripheral or memory devices at programmed
addresses if they are appropriately deÞned. CS0 can be conÞgured to be the global
chip-select for the boot device.
Chip Select 6ÑThis output enables a peripheral or memory device at a programmed
address if deÞned appropriately in the BR6 and OR6 in the memory controller.
Card Enable 1 Slot BÑThis output enables even byte transfers when accesses to
the PCMCIA Slot B are handled under the control of the PCMCIA interface.
Chip Select 7ÑThis output enables a peripheral or memory device at a programmed
address if deÞned appropriately in the BR7 and OR7 in the memory controller.
Card Enable 2 Slot BÑThis output enables odd byte transfers when accesses to the
PCMCIA Slot B are handled under the control of the PCMCIA interface.
MPC860 PowerQUICC UserÕs Manual
Description
MOTOROLA