Motorola MPC860 PowerQUICC User Manual page 238

Part II. PowerPC Microprocessor Module
0
Level-1 Table Pointer (M_TWB)
18-Bit
Level-1 Table Base
18-Bit
20-Bit
20 for 1 Kbyte
20 for 4 Kbyte
18 for 16 Kbyte
13 for 512 Kbyte
9 for 8 Mbyte
Figure 9-5. Two-Level Translation Table (MD_CTR[TWAM] = 0)
During address translation, the msbs of the missed effective address are replaced by the
physical page address bits from the level-two page descriptor; the page size determines the
number of replaced bits as shown in Table 9-1. The remaining physical address bits come
directly from the effective address. When MD_CTR[TWAM] = 0, the tablewalk begins at
the level-one base address placed in M_TWB. The level-one table is indexed by EA[0Ð11]
to get the level-one page descriptor. For 8-Mbyte pages, there must be eight identical entries
in the level-one table for EA[9Ð11].
9-12
17 0
Level-1 Index
12-Bit
Level-1 Index
Level-1 Table
Level-1 Descriptor 0
Level-1 Descriptor 1
Level-1 Descriptor N
Level-1 Descriptor 4095
Level-2 Table Base
Level-2 Table
20-Bit
Level-2 Descriptor 0
Level-2 Descriptor 1
Level-2 Descriptor N
Level-2 Descriptor 1023
MPC860 PowerQUICC UserÕs Manual
Effective Address
11 12 21
Level-2 Index
00
12-Bit
10-Bit
Level-2 Index 00
10-Bit
Physical Page Address
Physical Address
22 31
Page Offset
12 for 1 Kbyte
12 for 4 Kbyte
14 for 16 Kbyte
19 for 512 Kbyte
23 for 8 Mbyte
Page Offset
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