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¥ Memory control attributesÑThe MPC860 supports cache inhibit (CI), writethrough
(WT), and guarded (G) attributes, deÞned in the PowerPC Virtual Environment
Architecture (VEA). The memory coherence (M) attribute is not supported; to
ensure memory coherency, conÞgure the page as cache-inhibited. Chapter 8,
ÒInstruction and Data Caches,Ó describes the effects of CI and WT attributes in the
MPC860.
The G attribute is used to map I/O devices that are sensitive to speculative
(out-of-order) accesses. An attempted speculative access to a page marked guarded
(G = 1) stalls until either the access is nonspeculative or is canceled by the core.
Attempting to fetch from guarded memory causes an implementation-speciÞc
instruction TLB error interrupt.
9.7 Translation Table Structure
The MMU hardware supports a two-level software tablewalk. Other table structures are not
precluded. Figure 9-4 shows the two-level translation table when MD_CTR[TWAM] = 1
(4-Kbyte resolution of protection).
MOTOROLA
Chapter 9. Memory Management Unit (MMU)
Part II. PowerPC Microprocessor Module
9-9
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