Motorola MPC860 PowerQUICC User Manual page 991

Table 37-21 describes LCTRL1 Þelds.
Bits Name
0Ð2
3Ð5
6Ð8 CTG
9Ð11 CTH
12Ð1 CRWE
3
14Ð1 CRWF
5
16Ð1 CSG
7
18Ð1 CSH
9
20 SUSG
21 SUSH
22Ð2 CGBMS
5
26Ð2 CHBMS
9
30Ð3
1
37.5.1.5 Load/Store Support AND-OR Control Register (LCTRL2)
The load/store support AND-OR control register (LCTRL2), shown in Figure 37-21, is
used to conÞgure load/store watchpoint operations.
Bit 0 1 2
Field LW0EN LW0IA LW0IADC
Bit 16 17 18
Field LW1LADC LW1LD LW1LDDC BRKNOMSK
Reset
R/W
SPR
Figure 37-20. Load/Store Support AND-OR Control Register (LCTRL2)
MOTOROLA
Table 37-21. LCTRL1 Field Descriptions
CTE Compare type, comparators EÐH. 0xxNot active (reset value)
100 Equal
CTF
101 Less than
110 Greater than
111 Not equal
Select match on read/write of comparators E and F.
0x DonÕt care (reset value)
10 Match on read
11 Match on write
Compare size, comparator G and H.
00 Reserved
01 Word
10 Half-word
11 Byte
Signed/unsigned operating mode for comparator G and H.
0 Unsigned
1 Signed
Byte mask for comparator G and H.
K 0000 All bytes are not masked
0001 Last byte of the word is masked
É
K
1111 All bytes are masked
Ñ Reserved
3 4 5 6
LW0LA LW0LADC LW0LD LW0LDDC LW1EN
19 20 21 22
0000_0000_0000_0000
Chapter 37. System Development and Debugging
Description
7 8 9 10 11
LW1IA
23 24 25 26 27
Ñ DLW0EN DLW1EN SLW0EN SLW1EN
R/W
157
Part VI. Debug and Test
12 13 14 15
LW1IADC LW1LA
28 29 30 31
37-41