Motorola MPC860 PowerQUICC User Manual page 236

Part II. PowerPC Microprocessor Module
0
Level-1 Table Pointer (M_TWB)
20-Bit
Level-1 Table Base
20-Bit
20-Bit
20 for 4 Kbyte
18 for 16 Kbyte
13 for 512 Kbyte
9 for 8 Mbyte
Figure 9-4. Two-Level Translation Table (MD_CTR[TWAM] = 1)
When MD_CTR[TWAM] = 1, the tablewalk begins at the level-one base address in
M_TWB. EA[0Ð9] indicates the level-one page descriptor. As shown in Table 9-1, an
8-Mbyte page requires two identical entries in the level-one table, one for bit 9 = 0 and one
for bit 9 = 1.
9-10
19 0
Level-1 Index
10-Bit
Level-1 Index
Level-1 Table
Level-1 Descriptor 0
Level-1 Descriptor 1
Level-1 Descriptor N
Level-1 Descriptor 1023
Level-2 Table Base
Level-2 Table
20-Bit
Level-2 Descriptor 0
Level-2 Descriptor 1
Level-2 Descriptor N
Level-2 Descriptor 1023
MPC860 PowerQUICC UserÕs Manual
Effective Address
9 10 19 20
Level-2 Index
00
10-Bit
10-Bit
Level-2 Index 00
10-Bit
Physical Page Address
Physical Address
31
Page Offset
12 for 4 Kbyte
14 for 16 Kbyte
19 for 512 Kbyte
23 for 8 Mbyte
Page Offset
MOTOROLA