Table of Contents
Advertisement
Table 19-1 shows the order in which the CP handles requests from peripherals from highest
to lowest priority.
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1
See the RCCR[DRQP] description in Section 19.5.1, ÒRISC Controller
ConÞguration Register (RCCR).Ó
MOTOROLA
Table 19-1. Peripheral Prioritization
Reset in the CPCR or SRESET
SDMA bus error
Commands issued to the CPCR
IDMA emulation: DREQ0 and DSP1 (defaultÑoption 1)
IDMA emulation: DREQ1 and DSP2 (defaultÑoption 1)
SCC1 Rx
SCC1 Tx
SCC2 Rx
SCC2 Tx
SCC3 Rx
SCC3 Tx
SCC4 Rx
SCC4 Tx
IDMA emulation: DREQ0 and DSP1 (option 2)
IDMA emulation: DREQ1 and DSP2 (option 2)
SMC1 Rx
SMC1 Tx
SMC2 Rx
SMC2 Tx
SPI Rx
SPI Tx
2
I
C Rx
2
I
C Tx
PIP
RISC timer table
IDMA emulation: DREQ0 and DSP1 (option 3)
IDMA emulation: DREQ1 and DSP2 (option 3)
Chapter 19. Communications Processor
Part V. The Communications Processor Module
Request
1
1
1
1
1
1
19-3
Advertisement
Table of Contents
