Motorola MPC860 PowerQUICC User Manual page 974

Part VI. Debug and Test
¥ Instruction breakpoint. Recognized only when MSR[RI] = 1, when breakpoints are
maskable. Nonmaskable breakpoints are always recognized.
¥ Load/store breakpoint. Recognized only when MSR[RI] = 1, when breakpoints are
maskable. Nonmaskable breakpoints are always recognized.
¥ Maskable breakpoint from the development port generated by external modules are
recognized only when MSR[RI] = 1.
¥ Development port nonmaskable interrupt resulting from a debug station request.
Useful in some catastrophic events like an endless loop when MSR[RI] = 0. This
may cause the machine to enter a nonrestartable state. See Section 7.1.5,
ÒRecoverability after an Exception.Ó
The processor enters debug mode when at least one ICR bit is set, the corresponding DER
bit is enabled, and debug mode is enabled. When debug mode is enabled and an enabled
event occurs, the processor waits until its pipeline is empty before fetching instructions
from the development port. Section Chapter 7, ÒExceptions,Ó gives the exact SRR0 and
SRR1 values. If the core is in debug mode, the freeze indication is asserted, causing any
properly programmed peripheral to stop. The development port should read the value of the
ICR to get the cause of the debug mode entry. Reading the ICR clears all of its bits.
37.3.1.3 Debug Mode Indication
The fact that the core is in debug mode is broadcast to the external world using the value
0b11 on the VFLS pins. Debug mode indication will also be given on the FRZ pin. Note,
however, that the FRZ indication can also be used by software monitors, as described in
Section 37.4, ÒSoftware Monitor Debugger Support.Ó
37.3.1.4 Checkstop State and Debug Mode
The core enters checkstop state if the machine check interrupt is disabled (MSR[ME] = 0)
and a machine check interrupt is detected. However, if DER[CKSTPE] is also set, the core
enters debug mode rather then the checkstop state. Table 37-9 shows the various actions the
core can take when a machine check interrupt is detected.
Table 37-9. Checkstop State and Debug Mode
MSR[M Debug Mode
E] Enable
0 0
1 0
0 1
0 1
1 1
1 1
37-24
DER[CHSTPE DER[MCIE
] ]
X X
X X
0 X
1 X
X 0
X 1
MPC860 PowerQUICC UserÕs Manual
Core Response to Machine Check
Interrupt
Enter the checkstop state
Branch to machine check interrupt
Enter checkstop state
Enter debug mode
Branch to machine check interrupt
Enter debug mode
ICR Value
0x20000000
0x10000000
0x20000000
0x20000000
0x10000000
0x10000000
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