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Clock
Address
TS
TA
CS
R/W
WE
OE
Data
Figure 16-22. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1)
When TRLX and CSNT are set in a write-memory access, the strobe line, WE is negated
one clock earlier than in the normal case. If ACS ¹ 0, CS is also negated one clock earlier,
as shown in Figure 16-23 and Figure 16-24. When a bank is selected to operate with
external transfer acknowledge (SETA and TRLX = 1), the memory controller does not
support external devices that provide TA to complete the transfer with zero wait states. The
minimum access duration in this case is 3 clock cycles.
MOTOROLA
ACS = 10
Chapter 16. Memory Controller
Part IV. Hardware Interface
ACS = 11
16-23
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