Motorola MPC860 PowerQUICC User Manual page 854

Part V. The Communications Processor Module
Table 32-3 describes I2BRG Þelds.
Bits Name
0Ð7 DIV Division ratio 0Ð7. SpeciÞes the divide ratio of the BRG divider in the I
the prescaler is divided by 2 * ([DIV0ÐDIV7] + 3) and the clock has a 50% duty cycle. DIV must be
programmed to a minimum value of 3 if the digital Þlter is disabled and 6 if it is enabled.
32.4.4 I C Event/Mask Registers (I2CER/I2CMR)
2
The I 2 C event register (I2CER) is used to generate interrupts and report events. When an
event is recognized, the I
cleared by writing onesÑwriting zeros has no effect. Setting a bit in the I
(I2CMR) enables and clearing a bit masks the corresponding interrupt. Unmasked I2CER
bits must be cleared before the CPM clears internal interrupt requests. Figure 32-9 shows
both registers.
Bit 0
Field
Reset
R/W
Addr
Figure 32-9. I
Table 32-4 describes the I2CER/I2CMR Þelds.
Bits Name
0Ð2 Ñ Reserved and should be cleared.
3 TXE Tx error. Set when an error occurs during transmission.
4 Ñ Reserved and should be cleared.
5 BSY Busy. Set after the Þrst character is received but discarded because no Rx buffer is available.
6 TXB Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Two character
times must elapse to guarantee that all data has been sent.
7 RXB Rx buffer. Set after the last character is written to the Rx buffer and the RxBD is closed.
32.4.5 I 2 C Command Register (I2COM)
2
The I C command register, shown in Figure 32-10, is used to start I
master or slave mode.
32-8
Table 32-3. I2BRG Field Descriptions
2
C controller sets the corresponding I2CER bit. I2CER bits are
1 2
Ñ
0x870(I2CER)/0x874 (I2CMR)
2
C Event/Mask Registers (I2CER/I2CMR)
Table 32-4. I2CER/I2CMR Field Descriptions
MPC860 PowerQUICC UserÕs Manual
Description
3 4
TXE Ñ BSY
0000_0000
R/W
Description
2
C clock generator. The output of
2
C mask register
5 6 7
TXB RXB
2
C transfers and to select
MOTOROLA