Motorola MPC860 PowerQUICC User Manual page 496

Part IV. Hardware Interface
16.9.2 Page Mode Extended Data-Out Interface Example
Figure 16-63 shows the conÞguration for a 1-Mbyte, 32-bit wide memory system using two
256K x 16-bit page mode EDO DRAMs. Also shown is the physical connection between
UPMB and the EDO DRAMs. The CS2 signal controlled by BRx is connected to both RAS
signals. The BS_B[0Ð1] signals map to D[0Ð15] and BS_B[2Ð3] map to D[16Ð31]. For this
connection, GPL_B1 is connected to the memory device OE pins. The refresh rate
calculation is based on a 25-MHz baud rate generator clock and the DRAM that requires a
512-cycle refresh every 8 ms.
This system has no external masters, and thus the MPC860 is conÞgured to perform address
multiplexing internally.
MPC860
BS_B[0Ð3]
CS2
R/W
GPL_B1
A[21Ð29]
D[0Ð31]
Figure 16-63. EDO DRAM Interface Connection
Follow these steps to conÞgure a system for EDO DRAM:
1. Determine the system architecture, which includes the MPC860 and the memory
system as shown in the example in Figure 16-64.
2. The blank work sheet in Figure 16-70 can be used for timing diagrams. The timing
diagrams in Figure 16-64 through Figure 16-69 can be used as a reference.
3. Translate the timing diagrams into RAM words for each memory access type. The
bottom half of the Þgures show the RAM array contents that handle each of the
possible cycles; each column represents a different word in the RAM array. A blank
cell indicates a donÕt care bit (typically programmed to logic 1 to conserve power).
16-70
MT4C16270
256K x 16
2-Bit
RAS
BS_B0
CASL
BS_B1
CASH
WE
OE
A[0Ð8]
D[0Ð15]
D[0Ð15]
MPC860 PowerQUICC UserÕs Manual
MT4C16270
2-Bit
RAS
BS_B2
CASL
BS_B3
CASH
WE
OE
A[0Ð8]
D[16Ð31]
8-Bit
256K x 16
D[0Ð15]
8-Bit
MOTOROLA