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Motorola ColdFire MCF5281 User Manual

Motorola microcontroller user's manual.
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MCF5282UM/D
Rev. 2
1/2004
MCF5282 ColdFire
®
Microcontroller User's Manual
Devices Supported:
MCF5281

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   Summary of Contents for Motorola ColdFire MCF5281

  • Page 1 MCF5282UM/D Rev. 2 1/2004 MCF5282 ColdFire ® Microcontroller User’s Manual Devices Supported: MCF5281...
  • Page 2 Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
  • Page 3 Enhanced Multiply-Accumulate Unit (EMAC) ColdFire Flash Module (CFM) System Control Module (SCM) Interrupt Controller Modules Edge Port Module (EPORT) External Interface Module (EIM) Synchronous DRAM Controller Module Fast Ethernet Controller (FEC) Programmable Interrupt Timer (PIT) Modules General Purpose Timer (GPT) Modules Queued Serial Peripheral Interface Module (QSPI) General Purpose I/O Module Chip Configuration Module (CCM)
  • Page 4 Overview ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache Static RAM (SRAM) ColdFire Flash Module (CFM) Power Management System Control Module (SCM) Clock Module Interrupt Controller Modules Edge Port Module (EPORT) Chip Select Module External Interface Module (EIM) Signal Descriptions Synchronous DRAM Controller Module DMA Controller Module Fast Ethernet Controller (FEC) Watchdog Timer Module...
  • Page 5: Table Of Contents

    Queued Analog-to-Digital Converter (QADC) ... 1-15 Processor Pipelines ... 2-1 Processor Register Description ... 2-2 2.2.1 User Programming Model ... 2-2 2.2.2 EMAC Programming Model ... 2-5 2.2.3 Supervisor Programming Model... 2-5 MOTOROLA CONTENTS Title Chapter 1 Overview Chapter 2 ColdFire Core Contents Page...
  • Page 6 MAC Status Register (MACSR) ... 3-6 3.4.2 Mask Register (MASK) ... 3-11 EMAC Instruction Set Summary ... 3-12 3.5.1 EMAC Instruction Execution Times ... 3-12 3.5.2 Data Representation... 3-13 3.5.3 MAC Opcodes ... 3-14 CONTENTS Title Chapter 3 MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 7 Read Operations... 6-17 6.4.2 Write Operations... 6-17 6.4.3 Program and Erase Operations ... 6-17 6.4.4 Stop Mode... 6-22 6.4.5 Master Mode ... 6-23 MOTOROLA CONTENTS Title Chapter 4 Cache Chapter 5 Static RAM (SRAM) Chapter 6 ColdFire Flash Module (CFM)
  • Page 8 Bus Master Park Register (MPARK)... 8-12 System Access Control Unit (SACU)... 8-14 8.6.1 Overview... 8-14 8.6.2 Features... 8-14 8.6.3 Memory Map/Register Definition ... 8-15 viii CONTENTS Title Chapter 7 Power Management Chapter 8 System Control Module (SCM) MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 9 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63))... 10-11 10.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK). 10-15 10.4 Prioritization Between Interrupt Controllers ... 10-16 10.5 Low-Power Wakeup Operation ... 10-17 MOTOROLA CONTENTS Title Chapter 9 Clock Module Chapter 10 Interrupt Controller Modules...
  • Page 10 Misaligned Operands ... 13-14 14.1 Overview... 14-1 14.1.1 Single-Chip Mode... 14-17 14.1.2 External Boot Mode... 14-17 CONTENTS Title Chapter 11 Edge Port Module (EPORT) Chapter 12 Chip Select Module Chapter 13 Chapter 14 Signal Descriptions MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 11 15.3.3 DACR Initialization... 15-21 15.3.4 DMR Initialization... 15-22 15.3.5 Mode Register Initialization ... 15-23 15.3.6 Initialization Code... 15-24 16.1 Overview... 16-1 16.1.1 DMA Module Features ... 16-2 MOTOROLA CONTENTS Title Chapter 15 Chapter 16 DMA Controller Module Contents Page Number...
  • Page 12 Inter-Packet Gap (IPG) Time... 17-17 17.4.12 Collision Handling... 17-17 17.4.13 Internal and External Loopback... 17-17 17.4.14 Ethernet Error-Handling Procedure ... 17-18 17.5 Programming Model ... 17-20 CONTENTS Title Chapter 17 Fast Ethernet Controller (FEC) MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 13 Free-Running Timer Operation ... 19-7 19.6.3 Timeout Specifications ... 19-7 19.7 Interrupt Operation ... 19-8 20.1 Features ... 20-1 20.2 Block Diagram ... 20-2 MOTOROLA CONTENTS Title Chapter 18 Watchdog Timer Module Chapter 19 Chapter 20 General Purpose Timer Modules (GPTA and GPTB)
  • Page 14 Reset... 20-21 20.8 Interrupts ... 20-21 20.8.1 GPT Channel Interrupts (CnF) ... 20-22 20.8.2 Pulse Accumulator Overflow (PAOVF)... 20-22 20.8.3 Pulse Accumulator Input (PAIF) ... 20-22 20.8.4 Timer Overflow (TOF) ... 20-22 CONTENTS Title MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 15 22.5.2 QSPI Delay Register (QDLYR) ... 22-11 22.5.3 QSPI Wrap Register (QWR)... 22-12 22.5.4 QSPI Interrupt Register (QIR)... 22-13 22.5.5 QSPI Address Register (QAR) ... 22-14 MOTOROLA CONTENTS Title Chapter 21 DMA Timers (DTIM0–DTIM3) Chapter 22 (QSPI) Module Contents Page...
  • Page 16 Interface Features... 24-1 24.3 C System Configuration... 24-3 24.4 C Protocol ... 24-3 24.4.1 Arbitration Procedure ... 24-4 24.4.2 Clock Synchronization... 24-5 24.4.3 Handshaking ... 24-5 CONTENTS Title Chapter 23 UART Modules Chapter 24 C Interface MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 17 FlexCAN Initialization Sequence ... 25-16 25.4.11 Special Operating Modes... 25-17 25.4.12 Interrupts... 25-19 25.5 Programmer’s Model ... 25-20 25.5.1 CAN Module Configuration Register (CANMCR)... 25-20 25.5.2 FlexCAN Control Register 0 (CANCTRL0) ... 25-22 MOTOROLA CONTENTS Title Chapter 25 FlexCAN Contents Page Number xvii...
  • Page 18 27.4.3 External Trigger Input Signals... 27-6 27.4.4 Multiplexed Address Output Signals... 27-6 27.4.5 Multiplexed Analog Input Signals... 27-6 27.4.6 Voltage Reference Signals... 27-7 xviii CONTENTS Title Chapter 26 General Purpose I/O Module Chapter 27 MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 19 Analog Supply Filtering and Grounding ... 27-67 27.9.5 Accommodating Positive/Negative Stress Conditions ... 27-69 27.9.6 Analog Input Considerations ... 27-71 27.9.7 Analog Input Pins ... 27-73 27.10 Interrupts ... 27-75 27.10.1 Interrupt Operation ... 27-75 27.10.2 Interrupt Sources... 27-76 MOTOROLA CONTENTS Title Contents Page Number...
  • Page 20 Concurrent BDM and Processor Operation ... 29-39 29.7 Processor Status, DDATA Definition... 29-40 29.7.1 User Instruction Set ... 29-40 29.7.2 Supervisor Instruction Set... 29-44 29.8 Motorola-Recommended BDM Pinout... 29-46 CONTENTS Title Chapter 28 Reset Controller Module Chapter 29 Debug Support MCF5282 User’s Manual...
  • Page 21 Register Descriptions... 31-5 31.5 Functional Description... 31-7 31.5.1 JTAG Module ... 31-7 31.5.2 TAP Controller ... 31-7 31.5.3 JTAG Instructions... 31-8 31.6 Initialization/Application Information ... 31-11 31.6.1 Restrictions ... 31-11 MOTOROLA CONTENTS Title Chapter 30 Chapter 31 Contents Page Number...
  • Page 22 33.14 QSPI Electrical Specifications... 33-24 33.15 JTAG and Boundary Scan Timing... 33-25 33.16 Debug AC Timing Specifications... 33-27 xxii CONTENTS Title Chapter 32 Mechanical Data Chapter 33 Electrical Characteristics Appendix A Register Memory Map MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 23 CFM Supervisor Access Register (CFMSACC) ... 6-13 6-10 CFM Data Access Register (CFMDACC)... 6-14 6-11 CFM User Status Register (CFMUSTAT) ... 6-15 6-12 CFM Command Register (CFMCMD)... 6-16 6-13 Example Program Algorithm... 6-21 MOTOROLA ILLUSTRATIONS Title Illustrations Page Number xxiii...
  • Page 24 Chip Select Control Registers (CSCRn) ... 12-8 13-1 Signal Relationship to CLKOUT for Non-DRAM Access ... 13-2 13-2 Connections for External Memory Port Sizes ... 13-3 13-3 Chip-Select Module Output Timing Diagram ... 13-3 xxiv ILLUSTRATIONS Title MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 25 Byte Count Registers (BCRn)—BCR24BIT = 0... 16-7 16-8 DMA Control Registers (DCRn) ... 16-8 16-9 DMA Status Registers (DSRn) ... 16-10 17-1 FEC Block Diagram... 17-4 17-2 Ethernet Address Recognition—Receive Block Decisions ... 17-12 MOTOROLA ILLUSTRATIONS Title Illustrations Page Number...
  • Page 26 GPT Input Capture/Output Compare Select Register (GPTIOS) ... 20-5 20-3 GPT Input Compare Force Register (GPCFORC) ... 20-6 20-4 GPT Output Compare 3 Mask Register (GPTOC3M)... 20-6 20-5 GPT Output Compare 3 Data Register (GPTOC3D)... 20-7 xxvi ILLUSTRATIONS Title MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 27 UART Status Register (USRn) ... 23-7 23-5 UART Clock Select Register (UCSRn)... 23-8 23-6 UART Command Register (UCRn)... 23-9 23-7 UART Receive Buffer (URBn) ... 23-11 23-8 UART Transmit Buffer (UTBn) ... 23-12 MOTOROLA ILLUSTRATIONS Title Illustrations Page Number xxvii...
  • Page 28 25-11 Free Running Timer (TIMER)... 25-26 25-12 Rx Mask Registers (RXGMASK, RX14MASK, and RX15MASK) ... 25-27 25-13 FlexCAN Error and Status Register (ESTAT) ... 25-28 25-14 Interrupt Mask Register (IMASK)... 25-30 xxviii ILLUSTRATIONS Title MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 29 QADC Port QA Data Direction Register (DDRQA)... 27-11 27-7 Port QB Data Direction Register (DDRQB)... 27-11 27-8 QADC Control Register 0 (QACR0)... 27-12 27-9 QADC Control Register 1 (QACR1)... 27-14 27-10 QADC Control Register 2 (QACR2)... 27-17 MOTOROLA ILLUSTRATIONS Title Illustrations Page Number xxix...
  • Page 30 Star-Ground at the Point of Power Supply Origin ... 27-68 27-50 Input Signal Subjected to Negative Stress ... 27-69 27-51 Input Signal Subjected to Positive Stress ... 27-70 27-52 External Multiplexing of Analog Signal Sources ... 27-72 ILLUSTRATIONS Title MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 31 Command Sequence ... 29-31 29-33 Command/Result Formats... 29-32 RCREG 29-34 Command Sequence... 29-33 RCREG 29-35 Command/Result Formats... 29-34 WCREG 29-36 Command Sequence ... 29-35 WCREG 29-37 Command/Result Formats... 29-35 RDMREG 29-38 Command Sequence... 29-36 RDMREG MOTOROLA ILLUSTRATIONS Title Illustrations Page Number xxxi...
  • Page 32 33-17 Test Access Port Timing... 33-26 33-18 TRST Timing ... 33-26 33-19 BKPT Timing ... 33-27 33-20 Real-Time Trace AC Timing ... 33-28 33-21 BDM Serial Port AC Timing ... 33-28 xxxii ILLUSTRATIONS Title MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 33 ACR Field Descriptions... 4-11 SRAM Base Address Register ... 5-2 Typical RAMBAR Setting Examples... 5-4 CFM Configuration Field ... 6-5 FLASHBAR Field Descriptions ... 6-7 CFM Register Address Map ... 6-8 CFMCR Field Descriptions ... 6-9 MOTOROLA TABLES Title Tables Page Number xxxiii...
  • Page 34 Clock Out and Clock In Relationships ... 9-11 Charge Pump Current and MFD in Normal Mode Operation ... 9-13 Loss of Clock Summary ... 9-16 9-10 Stop Mode Operation... 9-17 10-1 Interrupt Priority Within a Level ... 10-3 xxxiv TABLES Title MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 35 Default Signal Functions After System Reset (External Boot Mode) ... 14-17 14-6 Transfer Size Encoding... 14-20 14-7 Processor Status Encoding... 14-32 15-1 SDRAM Commands ... 15-3 15-2 Synchronous DRAM Signal Connections ... 15-4 MOTOROLA TABLES Title Tables Page Number xxxv...
  • Page 36 7-Wire Mode Configuration ... 17-8 17-7 Destination Address to 6-Bit Hash ... 17-14 17-8 PAUSE Frame Field Specification ... 17-16 17-9 Module Memory Map ... 17-20 17-10 FEC Register Memory Map... 17-20 xxxvi TABLES Title MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 37 Signal Properties ... 20-3 20-3 GPT Modules Memory Map... 20-4 20-4 GPTIOS Field Descriptions ... 20-6 20-5 GPTCFORC Field Descriptions ... 20-6 20-6 GPTOC3M Field Descriptions ... 20-7 20-7 GPTOC3D Field Descriptions ... 20-7 MOTOROLA TABLES Title Tables Page Number xxxvii...
  • Page 38 UISRn/UIMRn Field Descriptions ... 23-14 23-10 UIPn Field Descriptions... 23-15 23-11 UOP1/UOP0 Field Descriptions ... 23-16 23-12 UART Module Signals ... 23-18 23-13 UART Interrupts ... 23-29 23-14 UART DMA Requests... 23-30 xxxviii TABLES Title MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 39 PFPAR Field Descriptions... 26-17 26-12 PJPAR Field Descriptions ... 26-18 26-13 PSDPAR Field Descriptions ... 26-19 26-14 PASPAR Field Descriptions ... 26-20 26-15 PEHLPAR Field Descriptions ... 26-21 26-16 PQSPAR Field Description ... 26-21 MOTOROLA TABLES Title Tables Page Number xxxix...
  • Page 40 Rev. A Shared BDM/Breakpoint Hardware ... 29-7 29-5 AATR Field Descriptions ... 29-8 29-6 ABLR Field Description ... 29-10 29-7 ABHR Field Description ... 29-10 29-8 CSR Field Descriptions ... 29-11 29-9 DBR Field Descriptions... 29-13 TABLES Title MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 41 33-4 PLL Electrical Specifications ... 33-6 33-5 QADC Absolute Maximum Ratings... 33-7 33-6 QADC Electrical Specifications (Operating) ... 33-7 33-7 QADC Conversion Specifications (Operating) ... 33-9 33-8 SGFM Flash Program and Erase Characteristics... 33-9 MOTOROLA TABLES Title Tables Page Number...
  • Page 42 Debug AC Timing Specification ... 33-27 CPU Space Register Memory Map... A-1 Module Memory Map Overview ... A-2 Register Memory Map ... A-3 xlii TABLES Title = 0 V, V = 5 V) ... 33-17 MCF5282 User’s Manual Page Number MOTOROLA...
  • Page 43: About This Book

    To locate any published errata or updates for this document, refer to the world-wide web at http://www.motorola.com/coldfire. Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products with the MCF5282.
  • Page 44 Access (DMA) controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail. xliv MCF5282 User’s Manual MOTOROLA...
  • Page 45 QADC module implemented on the MCF5282. • Chapter 28, “Reset Controller Module,” describes the operation of the reset controller module, detailing the different types of reset that can occur. MOTOROLA C module, including I C programming model registers. It also...
  • Page 46: Suggested Reading

    The following documentation provides useful information about the ColdFire architecture and computer architecture in general: • ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) • Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield • Computer Architecture: A Quantitative Approach, Second Edition, by John L.
  • Page 47 — ColdFire MCF5407 User’s Manual (MCF5407UM/AD) Additional literature on ColdFire implementations is being released as new processors become available. For a current list of ColdFire documentation, refer to the World Wide Web at http://www.motorola.com/ColdFire/. Conventions This document uses the following notational conventions: MNEMONICS In text, instruction mnemonics are shown in uppercase.
  • Page 48: Acronyms And Abbreviations

    Multiply accumulate unit, also Media access controller MBAR Memory base address register Most-significant byte Most-significant bit Multiplex No operation Operand execution pipeline Program counter PCLK Processor clock PLIC Physical layer interface controller Phase-locked loop xlviii Meaning MCF5282 User’s Manual MOTOROLA...
  • Page 49 Any address or data register Destination register w (used for MAC instructions only) Ry,Rx Any source and destination registers, respectively Index register i (can be an address or data register: Ai, Di) MOTOROLA Meaning Table ii. Notational Conventions Operand Syntax Opcode Wildcard...
  • Page 50 Signal displacement value, n bits wide (example: d16 is a 16-bit displacement) Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations) Arithmetic addition or postincrement indicator – Arithmetic subtraction or predecrement indicator Arithmetic multiplication Operand Syntax Register Names Port Name Miscellaneous Operands Operations MCF5282 User’s Manual MOTOROLA...
  • Page 51 Least significant bit (example: lsb of D0) Least significant byte Least significant word Most significant bit Most significant byte Most significant word Carry Negative Overflow Extend Zero MOTOROLA Operand Syntax Subfields and Qualifiers is a 16-bit displacement) Condition Code Register Bit Names About This Book...
  • Page 52: Revision History

    1.1/1-1 × Table 9-4/9-6 Table 9-4/9-6 Figure 10-13/10-12 Figure 10-1/10-7 Figure 10-3/10-8 Figure 10-5/10-9 14.2.4/14-22 Table 14-3/14-11 15.2/15-3 15.2.3.2/15-13 15.2.3.1/15-9 Figure 30-4/30-8 Chapter 29 Figure 29-41/29-46 Figure 32-1/32-2 Table 32-1/32-3 Table 33-3/33-4 Appendix A Figure 6-1/6-3 6.2/6-2 6.3.4.3/6-10 6.3.4.3/6-10 MOTOROLA...
  • Page 53 4. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.” MOTOROLA Table iii. Revision History Substantive Changes ÷...
  • Page 54 Table 23-9/23-14 Table 25-12/25-25 30.6.2/30-10 Table 27-4/27-12 Table 27-5/27-13 29.1/29-1 Figure 32-1/32-2 Table 32-1/32-3 Table 33-1/33-1 Table 33-9/33-10 + 10.” Table 33-11/33-11 Table 33-11/33-11 Figure 33-2/33-13 Figure 33-3/33-14 Figure 33-4/33-15 Table 33-12/33-16 Table 33-13/33-17 Table 33-13/33-17 33.12/33-20 Table 33-23/33-25 MOTOROLA...
  • Page 55 0–6.” Changed CSCRn to reflect that AA is set at reset. Removed final paragraph. The paragraph incorrectly states that the MCF5282 does not have a bus monitor. MOTOROLA Table iii. Revision History Substantive Changes About This Book Section/Page...
  • Page 56 MCF5282 User’s Manual Section/Page Table 14-3/14-11 Table 17-13/17-26 Chapter 19 19.6.3/19-7 × Figure 23-11/23-13 24.6.1/24-10 30.2.1/30-2 Table 32-2/32-7 Chapter 33 Table 33-1/33-1 Table 33-6/33-7 Figure 33-5/33-16 MOTOROLA...
  • Page 57: Overview

    — 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA, FEC) with standby power supply support — 512 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses (256 Kbytes on the MCF5281) – This product incorporates SuperFlash® technology licensed from SST. MOTOROLA Chapter 1. Overview...
  • Page 58 — Media-independent interface (MII) to transceiver (PHY) • FlexCAN 2.0B Module — Includes all existing features of the Motorola TOUCAN module — Full implementation of the CAN protocol specification version 2.0B – Standard data and remote frames (up to 109 bits long) –...
  • Page 59 — Two conversion command queues with a total of 64 entries — Sub-queues possible using pause mechanism — Queue complete and pause software interrupts available on both queues — Queue pointers indicate current location for each queue MOTOROLA C bus Chapter 1. Overview MCF5282 Key Features...
  • Page 60 — One dual-mode pulse accumulation channel per timer • Four periodic interrupt timers (PITs) — 16-bit counter — Selectable as free running or count down • Software watchdog timer — 16-bit counter — Low-power mode support MCF5282 User’s Manual MOTOROLA...
  • Page 61 — SDRAM controller supports 8-, 16-, and 32-bit wide memory devices — Glueless interface to SRAM devices with or without byte strobe inputs — Programmable wait state generator — 32-bit bidirectional data bus — 24-bit address bus MOTOROLA Chapter 1. Overview MCF5282 Key Features...
  • Page 62 — Up to 142 bits of general purpose I/O — Coherent 32-bit control — Bit manipulation supported via set/clear functions — Unused peripheral pins may be used as extra GPIO • JTAG support for system-level board testing MCF5282 User’s Manual MOTOROLA...
  • Page 63: Mcf5282 Block Diagram

    External Interface Module Chip Selects Interrupt Controller 0 Edgeport Interrupt Controller 1 DRAM Controller Clock Module (PLL) Figure 1-1. MCF5282 Block Diagram MOTOROLA JTAG Port Ports Module ColdFire V2 Core Flash Module UART0 UART1 UART2 Serial Serial Serial General General...
  • Page 64: Version 2 Coldfire Core

    16-byte line-sized fetch. The cache module includes a 16-byte line fill buffer used Table 1-1. Cache Configuration Tag Address Data Array Address [10:4] [10:4] 0, [9:4] 1, [9:4] MCF5282 User’s Manual [10:2] [10:2] 0, [9:2] 1, [9:2] MOTOROLA...
  • Page 65 It also provides a read datapath for non-core masters (for example, DMA). 1.1.1.4 Debug Module The ColdFire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator development tools. Through a standard MOTOROLA NOTE Chapter 1. Overview MCF5282 Key Features...
  • Page 66: System Control Module

    This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The debug interface is a superset of the BDM interface provided on Motorola’s 683xx family of parts.
  • Page 67: Chip Select

    JEDEC-compliant SDRAM devices. SRAS/SCAS address multiplexing is software configurable for different page sizes. To maintain refresh capability without conflicting with concurrent accesses on the address and data buses, SRAS, SCAS, DRAMW, SDRAM_CS[1:0], and SCKE are dedicated SDRAM signals. MOTOROLA Chapter 1. Overview MCF5282 Key Features 1-11...
  • Page 68: Test Access Port

    • Each channel programmable to normal (full-duplex), automatic echo, local loop-back, or remote loop-back mode • Automatic wake-up mode for multidrop applications • Four maskable interrupt conditions • All three UARTs have DMA request capability 1-12 MCF5282 User’s Manual MOTOROLA...
  • Page 69: Dma Timers (dtim0-dtim3)

    The four periodic interrupt timers (PIT0, PIT1, PIT2, PIT3) are 16-bit timers that provide precise interrupts at regular intervals with minimal processor intervention. Each timer can either count down from the value written in its PIT modulus register, or it can be a free-running down-counter. MOTOROLA Chapter 1. Overview MCF5282 Key Features 1-13...
  • Page 70: Software Watchdog Timer

    External reset on the RSTO pin is software-assertable independent of chip reset state. There are also software-readable status flags indicating the cause of the last reset, and LVD control and status bits for setup and use of LVD reset or interrupt. 1-14 MCF5282 User’s Manual MOTOROLA...
  • Page 71: Mcf5282-specific Features

    (DAC) resistor-capacitor array and a high-gain comparator. The digital control section contains queue control logic to sequence the conversion process and interrupt generation logic. Also included are the periodic/interval timer, control and MOTOROLA Chapter 1. Overview MCF5282-Specific Features 1-15...
  • Page 72 MCF5282-Specific Features status registers, the 64-entry conversion command word (CCW) table, and the 64-entry result table. 1-16 MCF5282 User’s Manual MOTOROLA...
  • Page 73: Coldfire Core

    Figure 2-1 is a block diagram showing the processor pipelines of a V2 ColdFire core. Instruction Fetch Pipeline DSOC Operand Execution Pipeline AGEX Figure 2-1. ColdFire Processor Core Pipelines MOTOROLA Instruction Address Generation Instruction Fetch Cycle FIFO Instruction Buffer Decode & Select, Operand Fetch...
  • Page 74: Processor Register Description

    Figure 2-2 illustrates the user programming model. The model is the same as the M68000 family microprocessors, consisting of the following registers: • 16 general-purpose 32-bit registers (D0–D7, A0–A7) • 32-bit program counter (PC) • 8-bit condition code register (CCR) MCF5282 User’s Manual MOTOROLA...
  • Page 75 PC or places a new value in the PC, as appropriate. For some addressing modes, the PC is used as a base address for PC-relative operand addressing. MOTOROLA Chapter 2. ColdFire Core Processor Register Description...
  • Page 76: User Programming Model

    Set to the value of the C bit for arithmetic operations; otherwise not affected. Description MCF5282 User’s Manual DATA REGISTERS ADDRESS REGISTERS USERSTACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER MOTOROLA...
  • Page 77: Emac Programming Model

    • 16-bit status register (SR) • 32-bit supervisor stack pointer (SSP) • 32-bit vector base register (VBR) • 32-bit cache control register (CACR) MOTOROLA MACSR MAC status register ACC0 MAC accumulator 0 ACC1...
  • Page 78: Supervisor Programming Model

    Supervisor/user state. Denotes whether the processor is in supervisor mode (S = 1) or user mode (S = 0). MCF5282 User’s Manual STATUS SUPERVISOR A7 STACK POINTER VECTOR BASE REGISTER CACHE CONTROL ACCESS CONTROL ACCESS CONTROL FLASH BASE ADDRESS REGISTER RAM BASE ADDRESS REGISTER MOTOROLA...
  • Page 79 Ay, USP; move to USP move.l USP, Ax; move from USP These instructions are described in the ColdFire Family Programmer’s Reference Manual. MOTOROLA Description Master/interrupt state. This bit is cleared by an interrupt exception, and can be set by software during execution of the RTE or move to SR instructions.
  • Page 80: Programming Model

    MOVEC instruction. Table 2-3. ColdFire CPU Registers Name CPU Space (Rc) CACR 0x002 ACR0, ACR1 0x004-0x005 Written with MOVEC Memory Management Control Registers Cache control register Access control registers 0 and 1 Processor General-Purpose Registers MCF5282 User’s Manual Register Name MOTOROLA...
  • Page 81: Additions To The Instruction Set Architecture

    Table 2-4 summarizes the new instructions added to Revision A+ ISA. For more details see Section 2.14, “ColdFire Instruction Set Architecture Enhancements.” MOTOROLA Additions to the Instruction Set Architecture Written with MOVEC...
  • Page 82: Exception Processing Overview

    (IACK) bus cycle to obtain the vector number from the interrupt controller. The IACK cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address. 2-10 Description MCF5282 User’s Manual MOTOROLA...
  • Page 83: Exception Vector Assignments

    All ColdFire processors support a 1024-byte vector table aligned on any 1 Mbyte address boundary (see Table 2-5). The table contains 256 exception vectors; the first 64 are defined by Motorola and the remaining 192 are user-defined interrupt vectors. Table 2-5. Exception Vector Assignments...
  • Page 84: Exception Stack Frame Definition

    Counter Next User-defined interrupts FS[3:2] VECTOR[7:0] FS[1:0] PROGRAM COUNTER[31:0] SSP @ 1st Instruction of Handler Original SSP - 8 Original SSP - 9 Original SSP - 10 Original SSP - 11 MCF5282 User’s Manual Assignment STATUS REGISTER Format Field MOTOROLA...
  • Page 85: Processor Exceptions

    An value. In addition, if an access error occurs during the execution of a MOVEM instruction loading from memory, any registers already updated before the fault occurs contain the operands from memory. MOTOROLA Definition Reserved Error on instruction fetch...
  • Page 86: Address Error Exception

    T-bit in the status register (SR[15] = 1), the completion of an instruction execution (for all but the STOP instruction) signals a trace exception. This functionality allows a debugger to monitor program execution. 2-14 development, ColdFire MCF5282 User’s Manual processors provide MOTOROLA...
  • Page 87: Unimplemented Line-a Opcode

    This special type of program interrupt is discussed in detail in Chapter 29, “Debug Support.” This exception is generated in response to a hardware breakpoint register trigger. The processor does not generate an IACK cycle but rather calculates the vector number internally (vector number 12). MOTOROLA Chapter 2. ColdFire Core Processor Exceptions 2-15...
  • Page 88: Rte And Format Error Exception

    Reset also aborts any processing in progress when the reset input is recognized. Processing cannot be recovered. 2-16 MCF5282 User’s Manual MOTOROLA...
  • Page 89: D0 Hardware Configuration Info

    Information loaded into D0 defines the processor hardware configuration as shown in Figure 2-8. Field Reset Field MAC DIV EMAC FPU MMU Reset Figure 2-8. D0 Hardware Configuration Info MOTOROLA NOTE 1100_1111_0010_0000 — 0110_0000_1000_0000 Chapter 2. ColdFire Core Processor Exceptions DEBUG...
  • Page 90: D0 Hardware Configuration Info Field Description

    0000 DEBUG_A (This is the value used for MCF5282) 0001 DEBUG_B 0010 DEBUG_C 0011 DEBUG_D 0100 DEBUG_E 0x5-0xF Reserved. Information loaded into D1 defines the local memory hardware configuration as shown in Figure 2-9. 2-18 Description MCF5282 User’s Manual MOTOROLA...
  • Page 91: D1 Hardware Configuration Info

    0011 2KB instruction cache. (This is the value used for MCF5282) 0100 4KB instruction cache. 0101 8KB instruction cache. 0110 16KB instruction cache. 0111 32KB instruction cache. 1000 64KB instruction cache. 0x9–0xF Reserved. MOTOROLA ICSIZ RAM0SIZ 0001_0011_1011_0000 DCSIZ RAM1SIZ 0001_0000_1000_0000...
  • Page 92 0001 512B data cache. 0010 1KB data cache. 0011 2KB data cache. 0100 4KB data cache. 0101 8KB data cache. 0110 16KB data cache. 0111 32KB data cache. 1000 64KB data cache. 0x9–0xF Reserved. 2-20 Description MCF5282 User’s Manual MOTOROLA...
  • Page 93: Instruction Execution Timing

    1. The operand execution pipeline (OEP) is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP does not wait for the instruction fetch pipeline (IFP) to supply opwords and/or extension words. MOTOROLA Description Chapter 2. ColdFire Core Instruction Execution Timing...
  • Page 94: Move Instruction Execution Times

    The nomenclature “xxx.wl” refers to both forms of absolute addressing, xxx.w and xxx.l. 2-22 Kbus Additional Size Operations C(R/W) Word Byte, Byte 2(1/0) if read 1(0/1) if write Long Byte, Word, Byte 3(2/0) if read 2(0/2) if write Long Word, Word 2(1/0) if read 1(0/1) if write MCF5282 User’s Manual MOTOROLA...
  • Page 95: Move Byte And Word Execution Times

    2(1/0) 2(1/1) ,An,Xi) 3(1/0) 3(1/1) (xxx).w 2(1/0) 2(1/1) (xxx).l 2(1/0) 2(1/1) ,PC) 2(1/0) 2(1/1) ,PC,Xi) 3(1/0) 3(1/1) #<xxx> 1(0/0) 2(0/1) MOTOROLA Destination (Ax)+ -(Ax) ,Ax) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1)
  • Page 96: Standard One Operand Instruction Execution Times

    — — — — — — — 5(0/1) — — — 4(1/0) 3(1/0) 1(0/0) 4(1/0) 3(1/0) 1(0/0) 3(1/0) 2(1/0) 1(0/0) (d8,An,Xn*SF) xxx.wl #xxx (d8,PC,Xn*SF) 4(1/0) 3(1/0) 1(0/0) 4(1/1) 3(1/1) — — — — 4(1/1) 3(1/1) — — — — MOTOROLA...
  • Page 97 1(0/0) ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) rems.l <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) remu.l <ea>,Dx sub.l <ea>,Rx 1(0/0) sub.l Dy,<ea> — MOTOROLA Standard Two Operand Instruction Execution Times Effective Address (d16,An) (An) (An)+ -(An) (d16,PC) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 3(1/1)
  • Page 98: Miscellaneous Instruction Execution Times

    — — — — — — — — — — — — — — 3(1/0) 4(1/0) 3(1/0) 5(2/0) — — MOTOROLA #xxx — — — #xxx — — 1(0/0) — 7(0/0) — — — — — — 3(0/0) 15(1/2) —...
  • Page 99: Emac Instruction Execution Times

    Raccext23,<ea>x 1(0/0) Effective address of (d16,PC) not supported Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional rounding is performed (MACSR[7:4] = 1---, -11-, --11) MOTOROLA Effective Address (An) (An)+ -(An) (d16,An) 6(1/0)
  • Page 100: Branch Instruction Execution Times

    Forward Backward Taken Not Taken Taken 2(0/0) — 2(0/0) 3(0/0) 1(0/0) 2(0/0) MCF5282 User’s Manual (d8,An,Xi*SF) xxx.wl #xxx (d8,PC,Xi*SF) — — — 4(0/0) 3(0/0) — 4(0/1) 3(0/1) — — — — — — — Backward Not Taken — 3(0/0) MOTOROLA...
  • Page 101 Not affected Instruction Field: • Register field—Specifies the destination data register, Dx. BITREV Opcode present MOTOROLA ColdFire Instruction Set Architecture Enhancements Bit Reverse Register (Supported Starting with ISA A+) V2, V3 Core (ISA_A) V4 Core (ISA_B) Chapter 2. ColdFire Core...
  • Page 102 (Supported Starting with ISA A+) new Dx[31:24] = old Dx[7:0] new Dx[23:16] = old Dx[15:8] new Dx[15:8] = old Dx[23:16] new Dx[7:0] = old Dx[31:24] V2, V3 Core (ISA_A) V4 Core (ISA_B) MCF5282 User’s Manual BYTEREV Register, Dx V2 Core (ISA_A+) MOTOROLA...
  • Page 103 — Codes: Instruction Field: • Destination Register field—Specifies the destination data register, Dx. Opcode present MOTOROLA ColdFire Instruction Set Architecture Enhancements Find First One in Register (Supported Starting with ISA A+) Old Dx[31:0] New Dx[31:0] 0b1---- . . . ---- 0x0000 0000 0b01--- .
  • Page 104 Z Set to the value of bit 2 of the immediate operand V Set to the value of bit 1 of the immediate operand C Set to the value of bit 0 of the immediate operand V2, V3 Core (ISA_A) V4 Core (ISA_B) MCF5282 User’s Manual STRLDSR V2 Core (ISA_A+) MOTOROLA...
  • Page 105: Enhanced Multiply-accumulate Unit (emac)

    EMAC improvements target three primary areas: • Improved performance of 32x32 multiply operations. • Addition of three more accumulators to minimize MAC pipeline stalls caused by exchanges between the accumulator and the pipeline’s general-purpose registers. MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC)
  • Page 106: Introduction To The Mac

    DSP operations. Consider a typical filtering operation where the filter is defined as in Figure 3-2. Operand Y Operand X Shift 0,1,-1 + / - Accumulator(s) MCF5282 User’s Manual MOTOROLA...
  • Page 107: General Operation

    For fractional operands, the entire 64-bit product is calculated and either truncated or rounded to the most-significant 40-bit result using the round-to-nearest (even) method before it is combined with the destination accumulator. MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) –...
  • Page 108: Fractional Alignment

    Product Extended Product Accumulator Extension Byte Upper [7:0] Figure 3-5. Signed and Unsigned Integer Alignment OperandY OperandX Accumulator [31:0] Figure 3-4. Fractional Alignment OperandY OperandX Extension Byte Lower [7:0] MCF5282 User’s Manual “0” Extension Byte Lower [7:0] Accumulator [31:0] MOTOROLA...
  • Page 109 The programming model includes a 16-bit mask register (MASK), which can optionally be used to generate an operand address during MAC + MOVE instructions. The application of this register with auto-increment addressing mode supports efficient implementation of circular data queues for memory operands. MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) General Operation...
  • Page 110: Memory Map/register Set

    ACC3 MAC accumulator 3 ACCext01 Extensions for ACC0 and ACC1 ACCext23 Extensions for ACC2 and ACC3 MASK MAC mask register Figure 3-6. EMAC Register Set 11–8 Prod/acc overflow flags Operational Mode PAVx OMC S/U 0000_0000_0000_0000_0000_0000_0000_0000 MCF5282 User’s Manual Flags MOTOROLA...
  • Page 111: Macsr Field Descriptions

    3–0 Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC, MSAC, and load operations; it is not affected by MULS and MULU instructions. MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) Description...
  • Page 112: Summary Of S/u, F/i, And R/t Control Bits

    No round on accumulator stores Signed, fractional Round on MAC.L and MSAC.L Round-to-32-bits on accumulator stores Unsigned, integer Signed, fractional Truncate on MAC.L and MSAC.L Round-to-16-bits on accumulator stores Signed, fractional Round on MAC.L and MSAC.L Round-to-16-bits on accumulator stores MCF5282 User’s Manual MOTOROLA...
  • Page 113 } macState; MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) /* R0.L = 0x8000 */ then Result = R0.U else Result = R0.U + 1 Memory Map/Register Set...
  • Page 114: Mask Register (mask)

    ; move the state to memory ; restore the state from memory ; disable rounding in the macsr ; restore the accumulators ; restore the accumulator extensions ; restore the address mask ; restore the macsr MCF5282 User’s Manual MOTOROLA...
  • Page 115 For auto-addressing modes of post-increment and pre-decrement, the calculation of the updated An value is also shown. Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular queue implementations. MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) Memory Map/Register Set 3-11...
  • Page 116: Emac Instruction Set Summary

    Loads the accumulator 0,1 extension bytes with a 32-bit operand Loads the accumulator 2,3 extension bytes with a 32-bit operand Writes the contents of accumulator 0,1 extension bytes into a CPU register Writes the contents of accumulator 2,3 extension bytes into a CPU register MCF5282 User’s Manual Description MOTOROLA...
  • Page 117: Data Representation

    • Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit. The remaining bits signify the first N-1 bits after the binary point. Given an N-bit number, a MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) Three-cycle...
  • Page 118: Mac Opcodes

    If the EMAC is in fractional mode (MACSR[F/I] is set), SF is ignored and no shift is performed. Because a product can overflow, the following guidelines are implemented: 3-14 – ∑ ⋅ – – MCF5282 User’s Manual – ⋅ (N-1) MOTOROLA...
  • Page 119 ((product[63:39] != 0x0000_00_0) && (product[63:39] != 0xffff_ff_1)) then { MACSR.PAVx = 1 MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) /* product overflow */ then if (product[63] == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 else if (MACSR.OMC == 1)
  • Page 120 = ACCx[47:0] - product[47:0] else result[47:0] = ACCx[47:0] + product[47:0] then /* accumulation overflow, saturationMode enabled */ if (result[47] == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 /* signed fractionals */ MCF5282 User’s Manual /* sign-extend */ MOTOROLA...
  • Page 121 MACSR.EV = 1 break; case 2: /* unsigned integers */ if (MACSR.OMC == 0 || MACSR.PAVx == 0) MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) then operandY[31:0] = {Ry[31:16], 0x0000} else operandY[31:0] = {Ry[15:0], then operandX[31:0] = {Rx[31:16], 0x0000}...
  • Page 122 /* 2-bit scale factor */ /* no scaling specified */ /* SF = “<< 1” */ /* reserved encoding */ /* SF = “>> 1” */ then result[47:0] = ACCx[47:0] - product[47:0] else result[47:0] = ACCx[47:0] + product[47:0] MCF5282 User’s Manual MOTOROLA...
  • Page 123 MACSR.Z = 0 if (ACCx[47:32] == 0x0000) then MACSR.EV = 0 else MACSR.EV = 1 break; MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) then result[47:0] = 0x0000_0000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */...
  • Page 124 EMAC Instruction Set Summary 3-20 MCF5282 User’s Manual MOTOROLA...
  • Page 125: Cache Features

    [10:2] addressing the storage array. For the split cache configuration, the cache tag and storage arrays are accessed in parallel. The msb of the tag array address is set for instruction fetches and cleared for operand fetches; fetch address bits [9:4] provide the rest of the tag MOTOROLA Chapter 4. Cache...
  • Page 126 Thus, the cache or the SRAM module can service subsequent requests while the remainder of the line is being fetched and loaded into the fill buffer. MCF5282 User’s Manual MOTOROLA...
  • Page 127: Cache Operation

    In this case, data accessed from the cache is simply discarded and no external memory references are generated. If the address is not mapped into the SRAM space, the cache handles the request in the normal fashion. MOTOROLA Buffer I or D Line...
  • Page 128: Memory Reference Attributes

    CACR[CPDI] is cleared. For the split data/instruction cache configuration, software directly controls bit 10 which selects whether an instruction cache or data cache line is being accessed. These invalidation operations can be initiated from the ColdFire core or the debug module. MCF5282 User’s Manual MOTOROLA...
  • Page 129: Reset

    = 01 fetch sequence = {0x4, 0x8, 0xC, 0x0} if miss address[3:2] = 10 fetch sequence = {0x8, 0xC, 0x0, 0x4} if miss address[3:2] = 11 fetch sequence = {0xC, 0x0, 0x4, 0x8} MOTOROLA Longword Address Bits Line Line Line Longword...
  • Page 130: Instruction Cache Operation As Defined By Cacr[31, 10]

    All instruction fetches are word or longword in size, and not loaded into the line-fill buffer Noncacheable Instruction fetch size is defined by Table 4-1 and loaded into the line-fill buffer, but are never written into the memory array. MCF5282 User’s Manual Description MOTOROLA...
  • Page 131: Cache Programming Model

    The CACR is a 32-bit write-only supervisor control register. It is accessed in the CPU address space via the MOVEC instruction with an Rc encoding of 0x002. The CACR can be read when in background debug mode (BDM). At system reset, the entire register is cleared. MOTOROLA Width Description Cache Control Register...
  • Page 132: Cache Control Register (cacr)

    1 Disable instruction caching Table 4-5 describes cache configuration and Table 4-6 describes how to set the cache invalidate all bit. — CINV DIDI DISD 0000_0000_0000_0000 CEIB DCM DBWE — 0000_0000_0000_0000 Description MCF5282 User’s Manual INVI INVD — DWP EUSP — CLNF MOTOROLA...
  • Page 133 Enable user stack pointer. See Section 2.2.3.2, “Supervisor/User Stack Pointers (A7 and OTHER_A7)" for more information on the dual stack pointer implementation. 0 Disable the processor’s use of the User Stack Pointer 1 Enable the processor’s use of the User Stack Pointer MOTOROLA Description Chapter 4. Cache Cache Programming Model...
  • Page 134: Cache Configuration As Defined By Cacr[31, 23, 22]

    Invalidate only 1 KByte data cache Data Cache Split Instruction Invalidate only 1 KByte instruction cache Data Cache Split Instruction/ No invalidate Data Cache Instruction Cache Invalidate 2 KByte instruction cache Data Cache Invalidate 2 KByte data cache MCF5282 User’s Manual Description Operation MOTOROLA...
  • Page 135: Access Control Registers (acr0, Acr1)

    Enable. The EN bit defines the ACR enable. Hardware reset clears this bit, disabling the ACR. 0 ACR disabled 1 ACR enabled MOTOROLA Longword Address Bits Line Line...
  • Page 136 WP bit, an access error terminates any attempted write with this bit set. 0 Read and write accesses permitted 1 Only read accesses permitted 1–0 — Reserved, should be cleared. 4-12 Description MCF5282 User’s Manual MOTOROLA...
  • Page 137: Static Ram (sram)

    See Chapter 5, “System Control Module (SCM)” for more information. SRAM Programming Model The SRAM programming model includes a description of the SRAM base address register (RAMBAR), SRAM initialization, and power management. MOTOROLA Chapter 5. Static RAM (SRAM)
  • Page 138: Sram Base Address Register (rambar)

    DMA or CPU has priority in lower 32k bank of memory. If bit is set, DMA has priority. If bit is reset, CPU has priority. Priority is determined according to the following table. NOTE: The Motorola-recommended setting for the priority bits is 00. Undefined PRI1 PRI2 SPV —...
  • Page 139: Sram Initialization

    3. After the data has been loaded into the SRAM, it may be appropriate to load a revised value into the RAMBAR with a new set of attributes. These attributes consist of the write-protect and address space mask fields. MOTOROLA Description Chapter 5. Static RAM (SRAM)
  • Page 140: Sram Initialization Code

    ;load RAMBASE + valid bit into D0. ;load RAMBAR and enable SRAM ;load pointer to SRAM ;load loop counter into D0 ;clear 4 bytes of SRAM ;decrement loop counter done, then RAMBAR[7:0] 0x2B 0x35 0x21 MCF5282 User’s Manual exit; else continue MOTOROLA...
  • Page 141 SRAM Programming Model MOTOROLA Chapter 5. Static RAM (SRAM)
  • Page 142 SRAM Programming Model MCF5282 User’s Manual MOTOROLA...
  • Page 143: Coldfire Flash Module (cfm)

    • Concurrent verify, program, and erase of all array blocks • Read-while-write capability • Optional interrupt on command completion • Flexible scheme for protection against accidental program or erase operations • Access restriction controls for both supervisor/user and data/program space operations MOTOROLA NOTE Chapter 6. ColdFire Flash Module (CFM)
  • Page 144: Block Diagram

    256 Kbytes of Flash space. Therefore, it takes two mass erase operations, one on mass erase block 0 and one on mass erase block 1, to erase the full 512K CFM Flash on the MCF5282. ) used for all module operations NOTE NOTE MCF5282 User’s Manual MOTOROLA...
  • Page 145: Cfm Block Diagram

    Mass Erase Block 0 (256 Kbytes) = Flash Physical Block 0 and Flash Physical Block 1. Mass Erase Block 1 (256 Kbytes) = Flash Physical Block 2 and Flash Physical Block 3 (MCF5282 only) MOTOROLA Chapter 6. ColdFire Flash Module (CFM)
  • Page 146: Memory Map

    3L[31] Memory Memory Array 3H Array 3L 3H[0] 3L[0] Flash Physical Block 1 1H[31] 1L[31] Memory Memory Array 1H Array 1L 1H[0] 1L[0] Each memory array = 64 Kbytes (16 bits wide × 32K) (32 bits wide × 32K) MOTOROLA...
  • Page 147: Cfm Configuration Field

    FLASHBAR, and return zeroes when read from the debug module. • The back door enable bit, FLASHBAR[BDE], is cleared at reset, disabling back door access to the Flash. MOTOROLA Chapter 6. ColdFire Flash Module (CFM) Size Back door comparison key Flash program/erase sector protection Blocks 0H/0L (see Section 6.3.4.4, “CFM Protection Register (CFMPROT)”)
  • Page 148 Flash is secured. If it is the part will always boot from internal Flash, since it will be marked as valid, regardless of what is done for chip configuration. NOTE NOTE NOTE MCF5282 User’s Manual MOTOROLA...
  • Page 149: Flash Base Address Register (flashbar)

    31–19 BA[31:18] 18–9 — 7–6 — 5–1 C/I, SC, SD, UC, MOTOROLA Chapter 6. ColdFire Flash Module (CFM) 0000_0000_0000_0000 — 0000_0001_0010_000 CPU + 0xC04 Description Base address field. Defines the 0-modulo-512K base address of the Flash module. By programming this field, the Flash may be located on any 512Kbyte boundary within the processor’s four gigabyte address space.
  • Page 150: Cfm Registers

    Bits 10 -5 in the CFMCR register are readable and writable with restrictions. Bits 23–16 Bits 15–8 CFMMCR CFMCLKD Reserved CFMSEC Reserved CFMPROT CFMSACC CFMDACC Reserved Reserved Reserved LOCK PVIE AEIE CBEIE CCIE KEYACC 0000_0000_0000_0000 IPSBAR + 0x1D_0000 MCF5282 User’s Manual Bits 7–0 Access Reserved — MOTOROLA...
  • Page 151: Cfm Clock Divider Register (cfmclkd)

    Figure 6-5. CFM Clock Divider Register (CFMCLKD) All bits in CFMCLKD are readable. Bit 7 is a read-only status bit, while bits 6–0 can only be written once. MOTOROLA Chapter 6. ColdFire Flash Module (CFM) Description Reserved, should be cleared.
  • Page 152: Cfm Security Register (cfmsec)

    Note: The SECSTAT bit reset value is determined by the security state of the Flash. All other bits in the register are loaded at reset from the Flash Security longword stored at the array base address + 0x0000_0414. Figure 6-6. CFM Security Register (CFMSEC) 6-10 Description divider. NOTE NOTE NOTE — See Note See Note IPSBAR + 0x1D_0008 MCF5282 User’s Manual MOTOROLA...
  • Page 153: Cfmsec Field Descriptions

    15–0 SEC[15:0] Security field. The SEC bits define the security state of the device; see below. The security features of the CFM are described in Section 6.5, “Flash Security Operation.” MOTOROLA Chapter 6. ColdFire Flash Module (CFM) Description SEC[15:0] 0x4AC8...
  • Page 154: Cfm Protection Register (cfmprot)

    The CFMPROT controls the protection of thirty-two 16-Kbyte Flash logical sectors in the 512-Kbyte Flash array. Figure 6-8 shows the association between each bit in the CFMPROT and its corresponding logical sector. 6-12 PROT See Note PROT See Note IPSBAR + 0x1D_0010 Description MCF5282 User’s Manual MOTOROLA...
  • Page 155: Cfmprot Protection Diagram

    Note: The CFMPROT register is loaded at reset from the Flash Supervisor/user Space Restrictions longword stored at the array base address + 0x0000_040C. Figure 6-9. CFM Supervisor Access Register (CFMSACC) MOTOROLA Chapter 6. ColdFire Flash Module (CFM) SECTOR 31 •...
  • Page 156: Cfm Data Access Register (cfmdacc)

    1 Logical sector is mapped in data address space. 0 Logical sector is mapped in data and program address space 6-14 Description DATA See Note DATA See Note IPSBAR + 0x1D_0018 Description MCF5282 User’s Manual MOTOROLA...
  • Page 157: Cfm User Status Register (cfmustat)

    See Section 6.4.3.4, “Flash User Mode Illegal Operations,” for details on what sets the ACCERR flag. 1 Access error has occurred 0 No failure — Reserved, should be cleared. MOTOROLA Chapter 6. ColdFire Flash Module (CFM) CCIF PVIOL ACCERR — 1100_0000...
  • Page 158: Cfm Command Register (cfmcmd)

    0x20 0x40 0x41 0x06 6-16 Description Flash physical blocks are not blank. 0000_0000 IPSBAR + 0x1D_0024 Description Name RDARY1 PGERS MASERS PGERSVER MCF5282 User’s Manual Description Erase verify (all 1s) Longword program Page erase Mass erase Page erase verify MOTOROLA...
  • Page 159: Cfm Operation

    Buffer empty and command completion are indicated by flags in the CFM user status register. Interrupts will be requested if enabled. MOTOROLA Chapter 6. ColdFire Flash Module (CFM) CFM Operation...
  • Page 160 400 kHz x (1 + (1 x 7)) 2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7)) 66 MHz 2 x (20 + 1) x (1 + (1 x 7)) MCF5282 User’s Manual = 20 = 196.43 kHz to 196.43 kHz which is MOTOROLA...
  • Page 161 Flash state machine sets the CCIF flag. The CBEIF flag is also set again, indicating that the address, data, and command buffers are ready for a new command sequence to begin. MOTOROLA Chapter 6. ColdFire Flash Module (CFM) WARNING is less than 150 kHz.
  • Page 162: Flash User Commands

    PROTECT bits are set for that block. Verify that the two 1024-byte pages are erased. If both pages are erased, the BLANK bit will be set in the CFMUSTAT register upon command completion. MCF5282 User’s Manual MOTOROLA...
  • Page 163: Example Program Algorithm

    ERROR CHECK ADDRESS, DATA, COMMAND BUFFER EMPTY CHECK BIT POLLING FOR COMMAND COMPLETION CHECK Figure 6-13. Example Program Algorithm MOTOROLA Chapter 6. ColdFire Flash Module (CFM) WRITE CFMCLKD READ CFMUSTAT CBEIF SET? WRITE PROGRAM DATA TO ARRAY ADDRESS NOTE: COMMAND SEQUENCE...
  • Page 164: Stop Mode

    1. The command in progress aborts 2. The Flash high voltage circuitry switches off and any pending command (CBEIF = 0) does not executed when the MCU exits stop mode. 6-22 MCF5282 User’s Manual MOTOROLA...
  • Page 165: Master Mode

    The CFM may be unsecured via one of two methods: 1. Executing a back door access scheme. 2. Passing an erase verify check. MOTOROLA Chapter 6. ColdFire Flash Module (CFM) NOTE WARNING...
  • Page 166: Back Door Access

    The CFM array is not accessible for any operations via the address and data buses during reset. If a reset occurs while any command is in progress that command will immediately abort. The state of any longword being programmed or any erase pages/physical blocks being erased is not guaranteed. 6-24 NOTE MCF5282 User’s Manual MOTOROLA...
  • Page 167: Interrupts

    Table 6-14 shows the CFM interrupt mechanism. Table 6-14. CFM Interrupt Sources Interrupt Source Command, data and address buffers empty All commands are completed Access error MOTOROLA Chapter 6. ColdFire Flash Module (CFM) Interrupt Flag Local Enable CBEIF CBEIE (CFMUSTAT) (CFMCR)
  • Page 168 Interrupts 6-26 MCF5282 User’s Manual MOTOROLA...
  • Page 169: Power Management

    Programming Model The PMM programming model consists of one register: • The low-power control register (LPCR) specifies the low-power mode entered when the STOP instruction is issued, and controls clock activity in this low-power mode. MOTOROLA Chapter 7. Power Management...
  • Page 170: Memory Map

    SCM to enter stop mode. Bits 23–16 Bits 15–8 Core Watchdog Low-Power Interrupt Control Register Control Register (CWCR) (LPICR) Reserved NOTE MCF5282 User’s Manual Bits 7–0 Access Core Watchdog Service Register (CWSR) Low-Power Control Register (LPCR) MOTOROLA...
  • Page 171: Low-power Interrupt Control Register (lpicr)

    XLPM_IPL[2:0] Exit low-power mode interrupt priority level. This field defines the interrupt priority level needed to exit the low-power mode.Refer to Table 7-3. 3–0 — Reserved, should be cleared. MOTOROLA NOTE XLPM_IPL[2:0] IPSBAR + 0x012 Description Chapter 7. Power Management Memory Map and Registers —...
  • Page 172: Low-power Control Register (lpcr)

    This bit has no effect if the RCR[LVDE] bit is a logic 0. 1 VREG Pseudo-Standby mode (LVD enabled on power down request). 0 VREG Standby mode (LVD disabled on power down request). Reserved, should be cleared. MCF5282 User’s Manual — LVDSE — MOTOROLA...
  • Page 173: Functional Description

    A wakeup event is required to exit a low-power mode and return to run mode. Wakeup events consist of any of these conditions: • Any type of reset • Any valid, enabled interrupt request MOTOROLA Table 7-5. Low-Power Modes LPMD[1:0] Mode...
  • Page 174: Wait Mode

    Stop mode must be entered in a controlled manner to ensure that any current operation is properly terminated. When exiting stop mode, most peripherals retain their pre-stop status and resume operation. The following subsections specify the operation of each module while in and when exiting low-power modes. MCF5282 User’s Manual MOTOROLA...
  • Page 175: Peripheral Behavior In Low-power Modes

    This system setup must meet the conditions specified in Section 7.3.1, “Low-Power Modes” for the core Watchdog interrupt to bring the part out of low-power mode. MOTOROLA NOTE Chapter 7. Power Management Functional Description...
  • Page 176 In wait and doze modes, the UART may generate an interrupt to exit the low-power modes. • Clearing the transmit enable bit (TE) or the receiver enable bit (RE) disables UART functions. • The UARTs are unaffected by wait mode and may generate an interrupt to exit this mode. NOTE MCF5282 User’s Manual MOTOROLA...
  • Page 177 In reference compare mode, where the output reference request interrupt enable (ORRI) bit of DTMR is set and the DTXMR[DMAEN] bit is cleared, an interrupt is issued when the timer counter reaches the reference value. MOTOROLA C resumes operation unless stop mode was Chapter 7. Power Management...
  • Page 178: Reset Controller

    In stop mode, the RSTI pin synchronization is disabled and asserting the external RSTI pin will asynchronously generate an internal reset and exit any low-power modes. Registers will lose current values and must be reconfigured from reset state if needed. 7-10 MCF5282 User’s Manual MOTOROLA...
  • Page 179: Clock Module

    During wakeup from stop mode, the Flash clock will always clock through 16 cycles before the system clocks are enabled. This allows the Flash module time to recover from the low-power mode. Thus, software may immediately continue to fetch instructions from the Flash memory. MOTOROLA Chapter 7. Power Management 7-11...
  • Page 180: Watchdog Timer

    (or clearing the QSTOP bit), returns the QADC to operation from the state prior to stop mode entry, but any conversions in progress are undefined and the QADC requires recovery time to stabilize the analog circuits before new conversions can be performed. 7-12 MCF5282 User’s Manual MOTOROLA...
  • Page 181 Exiting stop mode is done in one of the following ways: • Reset the FlexCAN (either by hard reset or by asserting the SOFT_RST bit in MCR). • Clearing the STOP bit in the MCR. MOTOROLA Chapter 7. Power Management Functional Description...
  • Page 182 FlexCAN's wake-up upon recessive to dominant edge may not conform to the standard CAN protocol, in the sense that the FlexCAN synchronization is shifted one time quanta from the required timing. This shift 7-14 MCF5282 User’s Manual MOTOROLA...
  • Page 183 MCU enters stop mode with a command in progress. Active commands are immediately aborted when the MCU enters stop mode. Do not execute the STOP instruction during program and erase operations. MOTOROLA NOTE Chapter 7. Power Management Functional Description 7-15...
  • Page 184: Summary Of Peripheral State During Low-power Modes

    Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled MCF5282 User’s Manual Stop Mode Stopped Stopped Stopped Stopped Stopped Stopped Stopped Stopped Stopped Stopped Stopped Enabled Stopped Enabled Enabled MOTOROLA...
  • Page 185 The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-power mode. Upon exit from halt mode, the previous low-power mode will be re-entered and changes made in halt mode will remain in effect. MOTOROLA Peripheral Status...
  • Page 186 Functional Description 7-18 MCF5282 User’s Manual MOTOROLA...
  • Page 187: System Control Module (scm)

    The SCM includes these distinctive features: • IPS base address register (IPSBAR) — Base address location for 1-Gbyte peripheral space — User control bits • Processor-local memory base address register (RAMBAR) • System control registers MOTOROLA Chapter 8. System Control Module (SCM)
  • Page 188: Memory Map And Register Definition

    [15:8] IPSBAR — RAMBAR — CWCR LPICR — MPARK PACR1 PACR2 — PACR5 — PACR8 GPACR1 — — — — — — MCF5282 User’s Manual [7:0] CWSR — PACR3 PACR6 — — — — — — — — — MOTOROLA...
  • Page 189: Register Descriptions

    5. Chip Selects This is the list of memory access priorities when viewed from the processor core. See Figure 8-1 and Table 8-2 for descriptions of the bits in IPSBAR. MOTOROLA Chapter 8. System Control Module (SCM) NOTE NOTE Register Descriptions...
  • Page 190: Memory Base Address Register (rambar)

    CPU space address 0xC05, and another located in the SCM at IPSBAR + 0x008. ColdFire core accesses to this memory are controlled by the processor-local copy of the RAMBAR, while module accesses are enabled by the SCM's RAMBAR. — — — — IPSBAR + 0x000 Description MCF5282 User’s Manual MOTOROLA...
  • Page 191: Rambar Field Description

    RAMBAR located in the processor’s CPU space must be initialized with the valid bit set before the CPU (or modules) can access the on-chip SRAM (see Chapter 5, “Static RAM (SRAM)” for more information. MOTOROLA Chapter 8. System Control Module (SCM) 0000_0000_0000_0000 0000_0000_0000_0000...
  • Page 192: Core Reset Status Register (crsr)

    The core watchdog timer can be enabled or disabled through CWCR[CWE]. By default it is disabled. If enabled, the watchdog timer requires the NOTE — CWDR See Note IPSBAR + 0x010 Description MCF5282 User’s Manual — MOTOROLA...
  • Page 193 The CWCR controls the software watchdog timer, time-out periods, and software watchdog timer transfer acknowledge. The register can be read at any time, but can be written only if the CWT is not pending. At system reset, the software watchdog timer is disabled. MOTOROLA Chapter 8. System Control Module (SCM) NOTE...
  • Page 194: Core Watchdog Control Register (cwcr)

    0000_0000 IPSBAR + 0x011 Description CWT [2:0] CWT Time-Out Period Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency MCF5282 User’s Manual CWTAVAL CWTIC MOTOROLA...
  • Page 195: Core Watchdog Service Register (cwsr)

    MBus masters (M0–M3 in Figure 8-6) has access to the external buses. The function of the arbitration logic is described in this section. MOTOROLA Chapter 8. System Control Module (SCM) Internal Bus Arbitration...
  • Page 196: Arbiter Module Functions

    Internal Bus Arbitration SRAM1 Internal Master Figure 8-6. Arbiter Module Functions 8-10 “back door” to SRAM and Flash MPARK RAMBAR MARB Internal Modules SDRAMC MCF5282 User’s Manual MOTOROLA...
  • Page 197: Overview

    M3 = 00 M2 =10 M1 = 11 M0 = 01 next +2 M3 = 01 M2 =11 M1 = 00 M0 = 10 next +3 M3 = 10 M2 =00 M1 = 01 M0 = 11 MOTOROLA Chapter 8. System Control Module (SCM) Internal Bus Arbitration 8-11...
  • Page 198: Bus Master Park Register (mpark)

    • Master 0 (M0): V2 ColdFire Core Field — Reset Field — FIXED TIMEOUT PRKLAST Reset Address Figure 8-7. Default Bus Master Park Register (MPARK) 8-12 M2_P_EN BCR24BIT M3_PRTY M2_PRTY M0_PRTY M1_PRTY 0011_0000_1110_0001 LCKOUT_TIME 0000_0000_0000_0000 IPSBAR + 0x01C MCF5282 User’s Manual — MOTOROLA...
  • Page 199: Mpark Field Description

    The initial state of the master priorities is M3 > M2 > M1 > M0. System software should guarantee that the programmed Mn_PRTY fields are unique, otherwise the hardware defaults to the initial-state priorities. MOTOROLA Chapter 8. System Control Module (SCM) Internal Bus Arbitration...
  • Page 200: System Access Control Unit (sacu)

    • Supervisor instruction fetch • Supervisor operand read • Supervisor operand write • User instruction fetch • User operand read • User operand write Instruction fetch accesses are associated with the execute attribute. 8-14 NOTE MCF5282 User’s Manual MOTOROLA...
  • Page 201: Memory Map/register Definition

    Module (SCM) is shown in Figure 8-8. The MPR, PACR, and GPACRs are 8 bits in width. Table 8-8. SACU Register Memory Map IPSBAR [31:28] [27:24] Offset 0x020 0x024 PACR0 MOTOROLA [23:20] [19:16] [15:12] — — — PACR1 Chapter 8. System Control Module (SCM)
  • Page 202: Master Privilege Register (mpr)

    A single PACR defines the access level for each of the two modules. These 8-16 [23:20] [19:16] [15:12] — PACR5 — PACR8 GPACR1 — — — — 0000_0011 IPSBAR + 0x020 Description MCF5282 User’s Manual [11:8] [7:4] [3:0] PACR6 — — — — — — — — — MPR[3:0] MOTOROLA...
  • Page 203: Peripheral Access Control Register (pacrn)

    The encodings for this field are shown in Table 8-11. Table 8-11. PACR ACCESSCTRL Bit Encodings Bits Table 8-12. Peripheral Access Control Registers (PACRs) IPSBAR Offset 0x024 0x025 0x026 MOTOROLA Chapter 8. System Control Module (SCM) ACCESS_CTRL1 LOCK0 0000_0000 IPSBAR + 0x24 + Offset Description Supervisor Mode...
  • Page 204: Gpacr Register

    PACR5 DTIM0 PACR6 DTIM2 PACR7 INTC0 — — PACR8 FEC0 NOTE 6–4 — ACCESS_CTRL 0000_0000 IPSBAR + 0x030, IPSBAR + 0x31 Figure 8-10. GPACR Register MCF5282 User’s Manual Modules Controlled ACCESS_CTRL0 — QSPI — DTIM1 DTIM3 INTC1 — — MOTOROLA...
  • Page 205: Gpacr Access_ctrl Bit Encodings

    1100 Read / Write / Execute 1101 Read / Write / Execute 1110 Read / Write 1111 Read / Write / Execute MOTOROLA Chapter 8. System Control Module (SCM) (GPACR) Field Descriptions Description Supervisor Mode No Access No Access Read...
  • Page 206: Gpacr Address Space

    0x07FF_FFFF 8-20 Modules Protected Ports, CCM, PMM, Reset controller, Clock, EPORT, WDOG, PIT0–PIT3, QADC, GPTA, GPTB, FlexCAN, CFM (Control) CFM (Flash module’s backdoor access for programming or access by a bus master other than the core) MCF5282 User’s Manual MOTOROLA...
  • Page 207: Clock Module

    2x to 9x the reference frequency and has a post divider capable of reducing this synthesized frequency without disturbing the PLL. The PLL reference can be either a crystal oscillator or an external clock. MOTOROLA Chapter 9. Clock Module...
  • Page 208: 1:1 Pll Mode

    Exit not caused by clock module, but clock sources are re-enabled and normal clocking Normal MCF5282 User’s Manual Mode Exit clocking resumes upon mode exit clocking resumes upon mode exit resumes upon mode exit Exit not caused by clock module MOTOROLA...
  • Page 209: Block Diagram

    Figure shows a block diagram of the entire clock module. The PLL block in this diagram is expanded in detail in Figure 9-2. EXTAL XTAL EXTERNAL CLOCK STPMD[1:0] STOP MODE Figure 9-1. Clock Module Block Diagram MOTOROLA CLKMOD[1:0] RSTOUT REFERENCE CLOCK PLLREF LOCEN LOLRE...
  • Page 210: Signal Descriptions

    Table 9-2. Signal Properties Function Oscillator or clock input Oscillator output System clock output Clock mode select inputs Reset signal from reset controller MCF5282 User’s Manual STPMD LOCKS LOCK TO RESET MODULE LOCS RFD[2:0] SCALED PLL CLOCK OUT PLL CLOCK MOTOROLA...
  • Page 211: Xtal

    Module Memory Map Table 9-3. Clock Module Memory Map IPSBAR Offset 0x0012_0000 0x0012_0002 S = CPU supervisor mode access only. MOTOROLA Register Name Synthesizer Control Register (SYNCR) Synthesizer Status Register (SYNSR) Chapter 9. Clock Module Memory Map and Registers Access...
  • Page 212: Synthesizer Control Register (syncr)

    0 No reset on loss of lock Note: In external clock mode, the LOLRE bit has no effect. MFD1 MFD0 LOCRE 0010_0001 FWKUP — STPMD1 0000_0000 IPSBAR + 0x0012_0000 Description MCF5282 User’s Manual RFD2 RFD1 RFD0 STPMD0 — — MOTOROLA...
  • Page 213 Note: In external clock mode, the LOCEN bit has no effect DISCLK Disable CLKOUT determines whether CLKOUT is driven. Setting the DISCLK bit holds CLKOUT low. 1 CLKOUT disabled 0 CLKOUT enabled MOTOROLA Description in normal PLL mode. (4x) (6x) (8x) 000 (÷...
  • Page 214: Synthesizer Status Register (synsr)

    Figure 9-4. Synthesizer Status Register (SYNSR) Description Operation During Stop Mode System Clocks Disabled Enabled Disabled Enabled Disabled Disabled Disabled Disabled PLLREF LOCKS LOCK See note 2 IPSBAR + 0x0012_0002 MCF5282 User’s Manual CLKOUT Enabled Enabled Enabled Disabled Enabled Disabled Disabled Disabled LOCS — MOTOROLA...
  • Page 215: Synsr Field Descriptions

    PLL. The power-on reset circuit uses the LOCK bit as a condition for releasing reset. If operating in external clock mode, LOCK remains cleared after reset. 1 PLL locked 0 PLL not locked MOTOROLA Description Chapter 9. Clock Module Memory Map and Registers...
  • Page 216: Functional Description

    Table 9-7 shows the clockout frequency to clockin frequency relationships for the possible system clock modes. 9-10 Description Clock Mode External clock mode 1:1 PLL mode Normal PLL mode with external clock reference Normal PLL mode with crystal reference MCF5282 User’s Manual MOTOROLA...
  • Page 217: Clock Operation During Reset

    MFD factor that can be paired with an RFD factor to provide the required frequency. 2. Write a value of RFD (from step 1) + 1 to the RFD field of the SYNCR. MOTOROLA PLL Options × 2(MFD + 2)/2 CAUTION Chapter 9.
  • Page 218: Pll Operation

    The reference clock comes from either the crystal oscillator or an external clock source. 9-12 NOTE 8-MHz CRYSTAL CONFIGURATIO C1 = C2 = 16 pF RF = 1 MΩ RS = 470 Ω XTAL SSSYN MCF5282 User’s Manual MOTOROLA...
  • Page 219: Charge Pump Current And Mfd In Normal Mode Operation

    MFD divides by. For example, if the MFD divides the VCO frequency by six, the PLL is frequency locked when the VCO MOTOROLA 0 ≤ MFD < 2 2 ≤ MFD < 6 6 ≤...
  • Page 220 Figure 9-6 shows the sequence for detecting locked and non-locked conditions. In external clock mode, the PLL is disabled and cannot lock. 9-14 MCF5282 User’s Manual MOTOROLA...
  • Page 221: Lock Detect Sequence

    (RSR) to determine if a loss of lock caused the reset. See Section 28.4.2, “Reset Status Register (RSR).” To exit reset in PLL mode, the reference must be present, and the PLL must achieve lock. MOTOROLA Loss of Lock Detected Set Tight Lock Criteria...
  • Page 222: Loss Of Clock Summary

    The LOC circuit monitors the reference and feedback inputs to the PFD. See Figure 9-5. 9-16 NOTE Reference Failure Alternate Clock Selected by LOC Circuit Until Reset PLL self-clocked mode None MCF5282 User’s Manual PLL Failure Alternate Clock Selected by LOC Circuit Until Reset PLL reference MOTOROLA...
  • Page 223: Stop Mode Operation

    X X X X — 0 0 0 Off Off 0 Lose lock, f.b. clock, reference clock X 0 0 Off Off 1 Lose lock, f.b. clock, reference clock MOTOROLA PLL Action MODE During Stop — Lose reference Stuck clock Regain ‘LK...
  • Page 224 LOCS not set because LOCEN = 0 ‘LC — — — ‘LC ‘LC LOCS not set because LOCEN = 0 ‘LC 0–>1 ‘LC ‘LC — — — 0–>1 ‘LC ‘LC — — — Reset immediately ‘LC — — — Reset immediately MOTOROLA...
  • Page 225 1 0 0 Off On 1 Lose lock, f.b. clock 1 0 0 On On 0 — 1 0 0 On On 1 — 1 0 1 On On X — MOTOROLA PLL Action MODE During Stop Regain ‘LK No regain Stuck Regain ‘LK...
  • Page 226 Comments — — — Reset immediately ‘LC — — — Reset immediately — — — ‘LC ‘LC — — — Reset immediately 0–>1 ‘LC ‘LC ‘LC — — Reset immediately — — — Wakeup without lock Wakeup without lock MOTOROLA...
  • Page 227 ‘LC=expecting previous value of LOCS before entering stop 1–>‘LC= current value is 1 until clock is regained which then will be the previous value before entering stop 1–> =current value is 1 until clock is regained but CLK is never expected to regain MOTOROLA PLL Action MODE During Stop —...
  • Page 228 Functional Description 9-22 MCF5282 User’s Manual MOTOROLA...
  • Page 229: Interrupt Controller Modules

    Level 7 interrupts are treated as non-maskable and edge-sensitive within the processor, while levels 1-6 are treated as level-sensitive and may be masked depending on the value of the SR[I] field. For MOTOROLA Chapter 10. Interrupt Controller Modules 10-1...
  • Page 230 During the execution of the service routine, the appropriate actions must be performed on the peripheral to negate the interrupt request. For more information on exception processing, see the ColdFire Programmer’s Reference Manual at http://www.motorola.com/coldfire 10-2 MCF5282 User’s Manual MOTOROLA...
  • Page 231: Interrupt Controller Theory Of Operation

    10.1.1.2 Interrupt Prioritization As an active request is detected, it is translated into the programmed interrupt level, and the resulting 7-bit decoded priority level (IRQ[7:1]) is driven out of the interrupt controller. MOTOROLA Chapter 10. Interrupt Controller Modules 68K/ColdFire Interrupt Architecture Overview...
  • Page 232 This design provides unique vector capability for all interrupt requests, regardless of the “complexity” of the peripheral device. Vector numbers 64-71, and 91-255 are unused. 10-4 then vector_number = then vector_number = then vector_number = then vector_number = en the bit position within the source to the actual MCF5282 User’s Manual MOTOROLA...
  • Page 233: Interrupt Controller Base Addresses

    ICR12 0x50 ICR16 0x54 ICR20 0x58 ICR24 0x5C ICR28 MOTOROLA Chapter 10. Interrupt Controller Modules Base Address IPSBAR + 0xC00 IPSBAR + 0xD00 IPSBAR + 0xF00 Bits[23:16] Bits[15:8] Interrupt Pending Register High (IPRH), [63:32] Interrupt Pending Register Low (IPRL), [31:1]...
  • Page 234: Register Descriptions

    Bits[23:16] Bits[15:8] ICR33 ICR34 ICR37 ICR38 ICR41 ICR42 ICR45 ICR46 ICR49 ICR50 ICR53 ICR54 ICR57 ICR58 ICR61 ICR62 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MCF5282 User’s Manual Bits[7:0] ICR35 ICR39 ICR43 ICR47 ICR51 ICR55 ICR59 ICR63 MOTOROLA...
  • Page 235: Interrupt Pending Register High (iprhn)

    IMRLn bit is set. 0 The corresponding interrupt source does not have an interrupt pending 1 The corresponding interrupt source has an interrupt pending — Reserved, should be cleared. MOTOROLA Chapter 10. Interrupt Controller Modules INT[63:48] 0000_0000_0000_0000 INT[47:32]...
  • Page 236: Interrupt Mask Register (imrhn, Imrln)

    1 The corresponding interrupt source is masked Field Reset Field Reset Figure 10-4. Interrupt Mask Register Low (IMRLn) 10-8 INT_MASK[63:48] 1111_1111_1111_1111 INT_MASK[47:32] 1111_1111_1111_1111 IPSBAR + 0xC08, 0xD08 Description INT_MASK[31:16] 1111_1111_1111_1111 INT_MASK[16:1] 1111_1111_1111_1111 IPSBAR + 0xC0C, 0xD0C MCF5282 User’s Manual MASKALL MOTOROLA...
  • Page 237: Interrupt Force Registers (intfrchn, Intfrcln)

    INTFRC Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes. 0 No interrupt forced on corresponding interrupt source 1 Force an interrupt on the corresponding source MOTOROLA Chapter 10. Interrupt Controller Modules Description INTFRCH[63:48]...
  • Page 238: Interrupt Force Register Low (intfrcln)

    0 There are no active interrupts at this level 1 There is an active interrupt at this level — Reserved 10-10 INTFRCL[31:16] 0000_0000_0000_0000 INTFRCL[16:1] 0000_0000_0000_0000 IPSBAR + 0xC14, 0xD14 Description IRQ[7:1] 0000_0000 IPSBAR + 0xC18, 0xD18 Description MCF5282 User’s Manual — — MOTOROLA...
  • Page 239: Interrupt Acknowledge Level And Priority Register (iacklprn)

    Failure to program the ICRnx registers in this manner can result in undefined behavior. If a specific interrupt request is completely unused, the ICRnx value can remain in its reset (and disabled) state. MOTOROLA Chapter 10. Interrupt Controller Modules LEVEL...
  • Page 240: Interrupt Control Register (icrnx)

    Write EPF3 = 1 Write EPF4 = 1 Write EPF5 = 1 Write EPF6 = 1 Write EPF7 = 1 Cleared when service complete Cleared when service complete Cleared when service complete Cleared when service complete MCF5282 User’s Manual Flag Clearing Mechanism MOTOROLA...
  • Page 241 PAOVF Pulse accumulator overflow Timer channel 0 Timer channel 1 Timer channel 2 Timer channel 3 MOTOROLA Chapter 10. Interrupt Controller Modules Source Description Not used Write IIF = 0 See QIR description Write CAP = 1 or REF = 1...
  • Page 242 Write PIF = 1 of write PMR Write PIF = 1 of write PMR Write PIF = 1 of write PMR Write CBEIF = 1 Cleared automatically Cleared automatically Cleared automatically Not Used MCF5282 User’s Manual Flag Clearing Mechanism MOTOROLA...
  • Page 243: Software And Level N Iack Registers (swiackr, L1iack-l7iack)

    The vector number is supplied as the data for the byte-sized IACK read cycle. In addition to providing the vector number, the interrupt controller also loads the level and priority number for the level into the IACKLPR register, where it may be retrieved later. MOTOROLA Chapter 10. Interrupt Controller Modules Source Description...
  • Page 244: Prioritization Between Interrupt Controllers

    INTC0 interrupt will be serviced first. If INTC1 has an active interrupt that has a higher level or priority than the highest INTC0 interrupt, then the INTC1 interrupt will be serviced first. 10-16 VECTOR 0000_0000 See Table 10-2 and Table 10-3 for register offsets Description MCF5282 User’s Manual MOTOROLA...
  • Page 245: Low-power Wakeup Operation

    SCM where it is combined with the wakeup signals from the other interrupt controller and then to the PLL module to re-enable the device’s clock trees and resume processing. MOTOROLA Chapter 10. Interrupt Controller Modules Low-Power Wakeup Operation NOTE...
  • Page 246 Low-Power Wakeup Operation 10-18 MCF5282 User’s Manual MOTOROLA...
  • Page 247: Introduction

    This section describes the operation of the EPORT module in low-power modes. For more information on low-power modes, see Chapter 7, “Power Management.” Table 11-1 shows EPORT module operation in low-power modes, and describes how this module may exit from each mode. MOTOROLA Stop Mode Edge Detect...
  • Page 248: Interrupt/general-purpose I/o Pin Descriptions

    Any IRQx Interrupt at or above level in LPICR Normal Any IRQx Interrupt at or above level in LPICR Level-sensing Only Any IRQx Interrupt set for level-sensing at or above level in LPICR NOTE MCF5282 User’s Manual Mode Exit MOTOROLA...
  • Page 249: Registers

    • The EPORT data register (EPDR) holds the data to be driven to the pins. • The EPORT pin data register (EPPDR) reflects the current state of the pins. • The EPORT flag register (EPFR) individually latches EPORT edge events. MOTOROLA EPORT Pin Assignment Register (EPPAR) EPORT Interrupt Enable Register (EPIER) EPORT Pin Data Register (EPPDR) Chapter 11.
  • Page 250: Eport Pin Assignment Register (eppar)

    EPORT Data Direction Register (EPDDR) Field EPDD7 Reset Address Figure 11-3. EPORT Data Direction Register (EPDDR) 11-4 EPPA5 EPPA4 EPPA3 0000_0000_0000_0000 IPSBAR + 0x0013_0000, 0x0013_0001 Description EPDD6 EPDD5 EPDD4 0000_0000 IPSBAR + 0x0013_0002 MCF5282 User’s Manual EPPA2 EPPA1 EPDD3 EPDD2 EPDD1 — MOTOROLA —...
  • Page 251: Eport Port Interrupt Enable Register (epier)

    0 Interrupt requests from corresponding EPORT pin disabled — Reserved, should be cleared. 11.4.2.4 Edge Port Data Register (EPDR) Field EPD7 Reset Address Figure 11-5. EPORT Port Data Register (EPDR) MOTOROLA Description EPIE6 EPIE5 EPIE4 0000_0000 IPSBAR + 0x0013_0003 Description EPD6 EPD5...
  • Page 252: Eport Port Pin Data Register (eppdr)

    Reset Address Figure 11-7. EPORT Port Flag Register (EPFR) 11-6 Description EPPD6 EPPD5 EPPD4 Current pin state IPSBAR + 0x0013_0005 Description EPF6 EPF5 EPF4 0000_0000 IPSBAR + 0x0013_0006 MCF5282 User’s Manual EPPD3 EPPD2 EPPD1 — EPF3 EPF2 EPF1 — MOTOROLA...
  • Page 253: Epfr Field Descriptions

    (EPPARx = 00), pin transitions do not affect this register. 1 Selected edge for IRQx pin has been detected. 0 Selected edge for IRQx pin has not been detected. — Reserved, should be cleared. MOTOROLA Chapter 11. Edge Port Module (EPORT) 11-7...
  • Page 254 Memory Map and Registers 11-8 MCF5282 User’s Manual MOTOROLA...
  • Page 255: Chip Select Module Signals

    These generated signals provide byte data select signals, which are decoded from the transfer size, A1, and A0 signals in addition to the programmed port size and burstability of the memory accessed, as Table 12-2 shows. MOTOROLA NOTE Description Chapter 12. Chip Select Module...
  • Page 256: Byte Enables/byte Write Enable Signal Settings

    Table 12-2 shows the interaction of the byte-enable/byte-write enables with related signals. Table 12-2. Byte Enables/Byte Write Enable Signal Settings Transfer Size Port Size Byte 8-bit 16-bit 32-bit Word 8-bit 16-bit 32-bit Longword 8-bit 16-bit 32-bit Line 8-bit 16-bit 32-bit 12-2 D[31:24] D[23:16] MCF5282 User’s Manual D[15:8] D[7:0] MOTOROLA...
  • Page 257: Chip Select Operation

    • If the address and attribute match both DACRs or a DACR and a CSAR, the operation is undefined. Table 12-3 shows the type of access as a function of match in the CSARs and DACRs. MOTOROLA Chapter 12. Chip Select Module Chip Select Operation...
  • Page 258: Connections For External Memory Port Sizes

    Byte 1 Driven, undefined Byte 2 Byte 3 Byte 0 Byte 1 Driven, undefined Byte 2 Byte 3 MCF5282 User’s Manual Type of Access External Defined by CSAR Defined by DACRs Undefined Undefined Undefined Undefined Undefined D[7:0] Byte 3 MOTOROLA...
  • Page 259: Chip Select Registers

    0x00_0094 0x00_0098 Chip select address register—bank 2 (CSAR2) 0x00_009C 0x00_00A0 0x00_00A4 Chip select address register—bank 3 (CSAR3) 0x00_00A8 MOTOROLA Boot Device/Data Port Size Internal (32-bit) External (16-bit) External (8-bit) External (32-bit) [23:16] [p. 12-6] Chip select mask register—bank 0 (CSMR0) [p. 12-7] Reserved Chip select control register—bank 0 (CSCR0)
  • Page 260: Chip Select Module Registers

    [p. 12-6] Chip select mask register—bank 6 (CSMR6) [p. 12-7] Reserved Chip select control register—bank 6 (CSCR6) Uninitialized 0x0B0 (CSAR4); 0x0BC (CSAR5); 0x0C8 (CSAR6) MCF5282 User’s Manual [15:8] [7:0] [p. 12-8] Reserved [p. 12-8] Reserved [p. 12-8] Reserved [p. 12-8] MOTOROLA...
  • Page 261: Chip Select Mask Registers (csmrn)

    1 Only read accesses are allowed. — Reserved, should be cleared. Alternate master. When AM = 0 during a DMA access, SC, SD, UC, and UD are don’t cares in the chip select decode. MOTOROLA Description 16 15 — Unitialized 0x0B4 (CSMR4);...
  • Page 262: Chip Select Control Registers (cscrn)

    0x08A (CSCR0); 0x096 (CSCR1); 0x0A2 (CSCR2); 0x0AE (CSCR3); Figure 12-4. Chip Select Control Registers (CSCRn) Table 12-8 describes CSCRn fields. 12-8 Description — AA PS1 PS0 BEM BSTR BSTW 11_11 — D19 D18 Uninitialized 0x0BA (CSCR4); 0x0C6 (CSCR5); 0x0D2 (CSCR6) MCF5282 User’s Manual — — — MOTOROLA...
  • Page 263: Cscrn Field Descriptions

    1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports and line writes to 8-, 16-, and 32-bit ports. 2–0 — Reserved, should be cleared. MOTOROLA Description Chapter 12. Chip Select Module Chip Select Registers 12-9...
  • Page 264 Chip Select Registers 12-10 MCF5282 User’s Manual MOTOROLA...
  • Page 265: Bus And Control Signals

    Table 13-1. ColdFire Bus Signal Summary Signal Name A[23:0] Address bus Byte selects CS[6:0] Chip selects D[31:0] Data bus Output enable Read/write SIZ[1:0] Transfer size MOTOROLA Chapter 13. External Interface Module (EIM) NOTE: Description CLKOUT Edge Rising Falling Falling Rising Falling Rising Rising 13-1...
  • Page 266: Bus Characteristics

    Data transfers between the MCF5282 and other devices involve the following signals: • Address bus (A[23:0]) • Data bus (D[31:0]) • Control signals (TS and TA) • CSn, OE, BS • Attribute signals (R/W, SIZ, and TIP) 13-2 Description MCF5282 User’s Manual CLKOUT Edge Rising Rising Rising MOTOROLA...
  • Page 267: Bus Cycle Execution

    13.4.1 Bus Cycle Execution When a bus cycle is initiated, the MCF5282 first compares the address of that bus cycle with the base address and mask configurations programmed for chip selects 0–7 MOTOROLA Chapter 13. External Interface Module (EIM) D[31:24]...
  • Page 268: Accesses By Matches In Cscrs And Dacrs

    CSCRs. If TA is not generated internally, the system must provide it externally. 13-4 Number of DACR Matches External Defined by CSCR External, burst-inhibited, 32-bit Defined by DACRs Undefined Undefined Multiple Undefined Multiple Undefined Multiple Undefined MCF5282 User’s Manual Type of Access MOTOROLA...
  • Page 269: Data Transfer Cycle States

    TS is negated on the rising edge of CLKOUT in S2. (skipped fast termination) Write The data bus is driven out of high impedance as data is placed on the bus on the rising edge of CLKOUT. MOTOROLA Chapter 13. External Interface Module (EIM) Fast Termination Wait States Table 13-3.
  • Page 270: Read Cycle

    13.4.3 Read Cycle During a read cycle, the MCF5282 receives data from memory or from a peripheral device. Figure 13-5 is a read cycle flowchart. 13-6 Description NOTE: MCF5282 User’s Manual MOTOROLA...
  • Page 271: Read Cycle Flowchart

    Note the following characteristics of a basic read: • In S3, data is made available by the external device on the falling edge of CLKOUT and is sampled on the rising edge of CLKOUT with TA asserted. MOTOROLA Chapter 13. External Interface Module (EIM) NOTE:...
  • Page 272: Write Cycle

    CLKOUT A[31:0], SIZ[1:0] CSn, BSn D[31:0] Figure 13-8. Basic Write Bus Cycle Table 13-3 describes the six states of a basic write cycle. 13-8 Decode address Store data on D[31:0] Assert TA Negate TA Write MCF5282 User’s Manual System MOTOROLA...
  • Page 273: Fast Termination Cycles

    Figure 13-9. Read Cycle with Fast Termination Figure 13-10 shows a write cycle with fast termination. CLKOUT A[31:0], SIZ[1:0] CSn, BSn D[31:0] Figure 13-10. Write Cycle with Fast Termination MOTOROLA Chapter 13. External Interface Module (EIM) Read Write Data Transfer Operation 13-9...
  • Page 274: Back-to-back Bus Cycles

    8-bit port, SIZ[1:0] = 00 for the first byte transfer and does not change. The CSCRs can be used to enable bursting for reads, writes, or both. MCF5282 memory space can be declared burst-inhibited for reads and writes by clearing the appropriate 13-10 MCF5282 User’s Manual MOTOROLA...
  • Page 275: Line Read Burst (2-1-1-1), External Termination

    (assertion of TS and TIP) and end (negation of TIP) of the transfer. CLKOUT A[31:0], SIZ[1:0] CSn, BSn, OE D[31:0] Figure 13-12. Line Read Burst (2-1-1-1), External Termination MOTOROLA Chapter 13. External Interface Module (EIM) A[3:2] Longword Accesses 0–4–8–C 4–8–C–0 8–C–0–4...
  • Page 276: Line Read Burst (2-1-1-1), Internal Termination

    The external device uses fast termination for subsequent transfers. 13-12 Read Read Read S4 S5 Read Read MCF5282 User’s Manual S11 S12 S13 Read Read Read MOTOROLA...
  • Page 277: Line Read Burst-inhibited, Fast Termination, External Termination

    A[31:0] Internal Termination A[31:0] External Termination SIZ[1:0] R/W, TIP CSn, OE, BSn D[31:0] Figure 13-16. Line Write Burst (2-1-1-1), Internal/External Termination MOTOROLA Chapter 13. External Interface Module (EIM) A[3:2] = 01 Line Read Read Basic Fast Write Data Transfer Operation...
  • Page 278: Misaligned Operands

    A byte operand is properly aligned at any address, a word operand is 13-14 S4 S5 Write Write A[3:2] = 01 A[3:2] = 10 Longword Write Fast MCF5282 User’s Manual Write Write A[3:2] = 11 Write Write Fast Fast MOTOROLA...
  • Page 279: Example Of A Misaligned Longword Transfer (32-bit Port)

    — Transfer 1 Transfer 2 Byte 1 Figure 13-20. Example of a Misaligned Word Transfer (32-Bit Port) MOTOROLA Chapter 13. External Interface Module (EIM) 24 23 16 15 — Byte 0 —...
  • Page 280 Misaligned Operands 13-16 MCF5282 User’s Manual MOTOROLA...
  • Page 281: Overview

    Active-low signals, such as SRAS and TA, are indicated with an overbar. 14.1 Overview Figure 14-1 shows the block diagram of the MCF5282 with the signal interface. MOTOROLA NOTE Chapter 14. Signal Descriptions 14-1...
  • Page 282: Mcf5282 Block Diagram With Signal Interfaces

    Timer A MCF5282 User’s Manual JTAG Port Debug Module DDATA[3:0] ColdFire V2 Core Flash VSTBY Module SRAM EMAC 2-Kbyte D-Cache/I-Cache UART2 Timer Watchdog Serial Modules Timer Module (DTIM0– DTIM3) General Purpose Timers QSPI FlexCAN Timer B (PIT0– PIT3) MOTOROLA Test Controller...
  • Page 283: Mcf5282 Signal Description

    Chip selects CS[6:0] SDRAM row SRAS address strobe SDRAM column SCAS address strobe MOTOROLA NOTE: Function External Memory Interface Define the address of external byte, word, longword, and 16-byte burst accesses. Data bus. Provide the general purpose data path between the MCU and all other devices.
  • Page 284 Serial output Ethernet data. Asserted to indicate a collision. Provides a timing reference for ERXDV, ERXD[3:0], and ERXER. MCF5282 User’s Manual Page 14-21 14-21 14-21 14-22 14-22 14-22 14-22 14-22 14-22 14-22 14-23 14-23 14-23 14-23 14-23 14-23 14-24 14-24 MOTOROLA...
  • Page 285 Transmit serial UTXD[2:0] data output Receive serial URXD[2:0] data input MOTOROLA Function Asserted to indicate that the PHY has valid nibbles present on the MII. Ethernet input data transferred from the PHY to the media access controller (when ERXDV is asserted).
  • Page 286 Provides single-bit communication for debug module commands (DSI). Provides serial data port for loading JTAG boundary scan, bypass, and instruction registers (TDI). MCF5282 User’s Manual Page 14-27 14-27 14-27 14-27 14-27 14-28 14-28 14-29 14-29 14-30 14-30 14-30 14-31 14-31 MOTOROLA...
  • Page 287 Standby power VSTBY Positive supply Ground Table 14-2 lists signals in alphabetical order by abbreviated name. MOTOROLA Function Provides single-bit communication for debug module responses (DSO). Provides serial data port for outputting JTAG logic data (TDO). JTAG test logic clock.
  • Page 288: Mcf5282 Alphabetical Signal Index

    ECOL Asserted to indicate a collision. ECRS Asserted to indicate that the transmit or receive medium is not idle. EMDC Provides a timing reference to the PHY for data transfers on the EMDIO signal. 14-8 Function MCF5282 User’s Manual MOTOROLA...
  • Page 289 Supplies positive power to the core logic and I/O pads. PST[3:0] Indicate core status. VRH, VRL High (VRH) and low (VRL) reference potentials for the analog converter. VDDA, VSSA Isolate the QADC analog circuitry from digital power supply noise. MOTOROLA Function Chapter 14. Signal Descriptions Overview 14-9...
  • Page 290 Asserted during the first CLKOUT cycle of a transfer when address and attributes are valid. UCTS[1:0] Signals UART that it can begin data transmission. URTS[1:0] Automatic UART request to send outputs. URXD[2:0] Receiver serial data inputs. 14-10 Function C interface. C interface. MCF5282 User’s Manual MOTOROLA...
  • Page 291: Mcf5282 Signals And Pin Numbers Sorted By Function

    CLKMOD1 RCON C6:B6:A5 A[23:21] C4:B4:A4:B3:A3 A[20:16] A2:B1:B2:C1: A[15:8] C2:C3:D1:D2 D3:D4:E1:E2: A[7:0] E3:E4:F1:F2 F3:G1:G2:G3: D[31:24] G4:H1:H2:H3 H4:J1:J2:J3: D[23:16] J4:K1:K2:K3 MOTOROLA Function Description Secondary Tertiary Reset — — Reset in — — Reset out Clock — — External clock/crystal in — —...
  • Page 292 UTXD2 Management channel clock PEH7 — MAC Transmit clock PEH6 — MAC Transmit enable PEH5 — MAC Transmit data MCF5282 User’s Manual Primary Internal Pull-up — — — — — — — — — — — — — — MOTOROLA...
  • Page 293 ERXDV ERXD0 ECRS A7:B7:C7 ETXD[3:1] ETXER A9:B9:C9 ERXD[3:1] ERXER CANRX CANTX QSPI_DOUT QSPI_DIN QSPI_CLK G14:G13:F16:F15 QSPI_CS[3:0] MOTOROLA Description Secondary Tertiary PEH4 — MAC Collision PEH3 — MAC Receive clock PEH2 — MAC Receive enable PEH1 — MAC Receive data PEH0 —...
  • Page 294 Timer A synchronization input SYNCB Timer B synchronization input SYNCA Timer A synchronization input SYNCB Timer B synchronization input MCF5282 User’s Manual Primary Internal Pull-up — — — — — — — — — — — — — — — — MOTOROLA...
  • Page 295 DTIN2 DTOUT2 DTIN1 DTOUT1 DTIN0 DTOUT0 Queued Analog-to-Digital Converter (QADC) AN52 AN53 AN55 AN56 JTAG_EN DSCLK TCLK BKPT MOTOROLA Description Secondary Tertiary DMA Timers PTC3 URTS1/ Timer 3 in URTS0 PTC2 URTS1/ Timer 3 out URTS0 PTC1 UCTS1/ Timer 2 in...
  • Page 296 Flash positive supply — — Flash module ground — — Standby power — — Positive supply — — Ground MCF5282 User’s Manual Primary Internal Description Pull-up MOTOROLA — — — — — — — — — — — — — — —...
  • Page 297: Single-chip Mode

    Table 14-4 will operate as described above. All other signals will default to GPIO inputs. Table 14-5. Default Signal Functions After System Signal A[23:0] D[31:0] BS[3:0] SIZ[1:0] MOTOROLA Reset Clock and Reset Signals — — XTAL CLKOUT Debug Support Signals —...
  • Page 298: Mcf5282 External Signals

    These pins are configured as GPIO ports A, B, C and D in single-chip mode. 14.2.1.3 Byte Strobes (BS[3:0]) The byte strobes (BS[3:0]) define the byte lane of data on the data bus. During accesses, 14-18 Reset High High High MCF5282 User’s Manual MOTOROLA...
  • Page 299 When the device is in normal mode, static bus sizing lets the programmer change data bus width between 8, 16, and 32 bits for each chip select. The SIZ[1:0] outputs specify the data access size of the current external bus reference as shown in Table 14-6. MOTOROLA Chapter 14. Signal Descriptions 14-19...
  • Page 300: Transfer Size Encoding

    This pin can also be configured as GPIO PE0 or SYNCB. 14.2.1.11 Chip Selects (CS[6:0]) Each chip select can be programmed for a base address location and for masking addresses, 14-20 Transfer Size Longword Byte Word 16-byte line NOTE: MCF5282 User’s Manual MOTOROLA...
  • Page 301: Sdram Controller Signals

    SDRAM memory blocks). These pins is configured as GPIO PSD[2:1] in single-chip mode. 14.2.2.5 SDRAM Clock Enable (SCKE) This output is the SDRAM clock enable. This pin is configured as GPIO PSD0 in single-chip mode. MOTOROLA Chapter 14. Signal Descriptions 14-21...
  • Page 302: Clock And Reset Signals

    (see Section 30.6, “Functional Description”). The internal configuration signals are driven to reflect the levels on the external configuration pins to allow for module configuration. 14.2.4.2 CLKMOD[1:0] The state of the CLKMOD[1:0] pins during reset determines the clock mode after reset. 14-22 MCF5282 User’s Manual MOTOROLA...
  • Page 303: External Interrupt Signals

    ETXD0 is the serial output Ethernet data and is only valid during the assertion of ETXEN. This signal is used for 10 Mbps Ethernet data. This signal is also used for MII mode data in conjunction with ETXD[3:1]. MOTOROLA Chapter 14. Signal Descriptions 14-23...
  • Page 304 When the ETXER output is asserted for one or more E_TXCLKs while ETXEN is also asserted, the PHY sends one or more illegal symbols. ETXER has no effect at 10 Mbps or when ETXEN is negated, and applies to MII mode operation. 14-24 MCF5282 User’s Manual MOTOROLA...
  • Page 305: Queued Serial Peripheral Interface (qspi) Signals

    14.2.7.4 QSPI Chip Selects (QSPI_CS[3:0]) The synchronous peripheral chip selects (QSPI_CS[3:0]) outputs provide QSPI peripheral chip selects that can be programmed to be active high or low. This pin can also be configured as GPIO PQS[6:3]. MOTOROLA Chapter 14. Signal Descriptions 14-25...
  • Page 306: Flexcan Signals

    The UTXD[1:0] pins can be configured as GPIO ports PUA2 and PUA0. The UTXD2 output is offered on 3 pins and is a secondary function of the EMDC/ GPIO port PAS4 pin, CANTX/GPIO port PAS2 pin, and SCL/GPIO port PAS0 pin. 14-26 MCF5282 User’s Manual MOTOROLA...
  • Page 307: General Purpose Timer Signals

    These pins can also be configured as GPIO PTB[3:0]. 14.2.11.3 External Clock Input (SYNCA/SYNCB) These pins are used to clear the clock for each of the two timers, and are provided as a means of synchronization to externally clocked or timed events. MOTOROLA Chapter 14. Signal Descriptions 14-27...
  • Page 308: Dma Timer Signals

    14.2.12.6 DMA Timer 2 Output (DTOUT2) The programmable DMA timer output (DTOUT2) pulse or toggle on various timer events. This pin can also be configured as GPIO PTC0, secondary function UCTS1, or secondary function UCTS0. 14-28 MCF5282 User’s Manual MOTOROLA...
  • Page 309: Analog-to-digital Converter Signals

    ANZ. This pin can also be configured as GPIO PQB3. 14.2.13.5 QADC Analog Input (AN52/MA0) This PQA signal is the direct analog input AN52. When using external multiplexing this MOTOROLA Chapter 14. Signal Descriptions 14-29...
  • Page 310: Debug Support Signals

    JTAG instruction register to choose the bypass instruction. When this occurs, JTAG logic is benign and does not interfere with normal MCF5282 functionality. Although TRST is asynchronous, Motorola recommends that it makes an 14-30 MCF5282 User’s Manual...
  • Page 311 Various JTAG operations occur on the rising or falling edge of TCK. Holding TCK high or low for an indefinite period does not cause JTAG test logic to lose state information. If TCK is not used, it must be tied to ground. MOTOROLA Chapter 14. Signal Descriptions 14-31...
  • Page 312: Test Signals

    Begin execution of RTE instruction Begin one-byte transfer on DDATA Begin two-byte transfer on DDATA Begin three-byte transfer on DDATA Begin four-byte transfer on DDATA Exception Processing Emulator-Mode Exception Processing Processor is stopped Processor is halted MCF5282 User’s Manual MOTOROLA...
  • Page 313: Power And Reference Signals

    This pin is used to provide standby voltage to the RAM array if VDD is lost. 14.2.16.8 Positive Supply (VDD) This pin supplies positive power to the core logic and I/O pads. 14.2.16.9 Ground (VSS) This pin is the negative supply (ground) to the chip. MOTOROLA Chapter 14. Signal Descriptions 14-33...
  • Page 314 MCF5282 External Signals 14-34 MCF5282 User’s Manual MOTOROLA...
  • Page 315: Definitions

    • SDRAM bank: An internal partition in an SDRAM device. For example, a 64-Mbit SDRAM component might be configured as four 512K x 32 banks. Banks are selected through the SDRAM component’s bank select lines. MOTOROLA Chapter 15. Synchronous DRAM Controller Module 15-1...
  • Page 316: Block Diagram And Major Components

    15-2 Data Generation Address Multiplexing Control Logic State Machine DRAM Control Register (DCR) Refresh Counter MCF5282 User’s Manual D[31:0] D[31:0] A[31:0] SCAS SRAS SCKE SDRAM_CS[1:0] DRAMW BS[3:0] MOTOROLA...
  • Page 317: Sdram Controller Operation

    Commands are issued to memory using specific encodings on address and control pins. Soon after system reset, a command must be sent to the SDRAM mode register to configure SDRAM operating parameters. MOTOROLA Chapter 15. Synchronous DRAM Controller Module Table 15-1. SDRAM Commands Definition executes;...
  • Page 318: Dram Controller Signals

    DRAM address and control register 0 (DACR0) [p. 15-6] DRAM mask register block 0 (DMR0) [p. 15-8] DRAM address and control register 1 (DACR1) [p. 15-6] DRAM mask register block 1 (DMR1) [p. 15-8] MCF5282 User’s Manual [7:0] — MOTOROLA...
  • Page 319: Dram Control Register (dcr)

    15.625 µs for each row (1031 bus clocks at 66 MHz). This operation is the same as in asynchronous mode. # of bus clocks = 1031 = (RC field + 1) x 16 RC = (1031 bus clocks/16) -1 = 63.44, which rounds to 63; therefore, RC = 0x3F. MOTOROLA Chapter 15. Synchronous DRAM Controller Module RTIM...
  • Page 320: Dram Address And Control Register (dacrn)

    — Reserved, should be cleared. 15-6 — — CASL — Uninitialized IPSBAR+0x048 (DACR0); 0x050 (DACR1) Description Parameter CASL= 00 command ACTV MCF5282 User’s Manual — IMRS Uninitialized Number of Bus Clocks CASL = 01 CASL= 10 CASL= 11 MOTOROLA —...
  • Page 321 DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the 2–0 — Reserved, should be cleared. MOTOROLA Chapter 15. Synchronous DRAM Controller Module Description Command Bit ) command. Setting IMRS generates a command finishes.
  • Page 322: Dram Controller Mask Registers (dmrn)

    WP — C/I AM SC SD UC UD V Uninitialized IPSBAR + 0x04C (DMR0), 0x054 (DMR1) Description MOVEC instruction or interrupt acknowledge cycle DMA master Any supervisor-only instruction access Any data fetched during the instruction access Any user instruction Any user data MCF5282 User’s Manual Access Definition MOTOROLA...
  • Page 323: General Synchronous Operation Guidelines

    SDRAM address lines are connected. Table 15-7. Generic Address Multiplexing Scheme Address Pin Row Address Column Address MOTOROLA Chapter 15. Synchronous DRAM Controller Module NOTE Notes Relating to Port Sizes 8-bit port only...
  • Page 324: Mcf5282 To Sdram Interface (8-bit Port,13-column Address Lines)

    Table 15-12. MCF5282 to SDRAM Interface (8-Bit Port,13-Column Address Lines) MCF5282 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 Pins Column SDRAM Pins 15-10 MCF5282 User’s Manual A9 A10 A11 A12 A9 A10 A11 A9 A10 A11 MOTOROLA...
  • Page 325: Mcf5282 To Sdram Interface (16-bit Port, 12-column Address Lines)

    Column SDRAM Pins Table 15-17. MCF5282 to SDRAM Interface (16-Bit Port, 12-Column Address Lines) MCF5282 Pins Column SDRAM Pins MOTOROLA Chapter 15. Synchronous DRAM Controller Module SDRAM Controller Operation A9 A10 A11 A12 A18 A20 A22 A23 A10 A11 15-11...
  • Page 326: Mcf5282 To Sdram Interface (32-bit Port, 11-column Address Lines)

    A15 A14 A13 A12 A11 A10 Pins Column SDRAM Pins Table 15-22. MCF5282 to SDRAM Interface (32-Bit Port, 11-Column Address Lines) MCF5282 Pins Column SDRAM Pins 15-12 A17 A19 A21 A22 A23 MCF5282 User’s Manual A9 A10 A11 A12 A10 A11 MOTOROLA...
  • Page 327: Mcf5282 To Sdram Interface (32-bit Port, 12-column Address Lines)

    In burst page mode, there are multiple read or write operations for every command in the SDRAM if the requested transfer size exceeds ACTV MOTOROLA Chapter 15. Synchronous DRAM Controller Module D[31:24] D[23:16] D[15:8]...
  • Page 328: Burst Read Sdram Access

    ) of 2 system clock cycles. Note that data is available The next bus cycle is initiated sooner, but cannot begin an delay completes. ACTV MCF5282 User’s Manual READ WRITE command is generated to prepare is equal to the read command is executed one cycle Column READ PALL MOTOROLA...
  • Page 329: Burst Write Sdram Access

    At this time, an internal refresh request flag is set and the counter begins counting down again. The DRAM controller completes any active burst operation and then performs operation. The DRAM controller then initiates a refresh cycle and clears the refresh PALL MOTOROLA Chapter 15. Synchronous DRAM Controller Module Column Column Column...
  • Page 330: Auto-refresh Operation

    SELF command is sent to the DRAM controller. Figure 15-9 shows the self-refresh operation. 15-16 is finished. Because both chip selects are active during the MCF5282 User’s Manual command is ACTV delay ACTV command is then ACTV SELFX MOTOROLA ACTV...
  • Page 331: Initialization Sequence

    DMR[BAM] if the mode register configuration does not fall in the address range determined by the address mask bits. After the mode register is set, DMR mask bits can be restored to their desired configuration. MOTOROLA Chapter 15. Synchronous DRAM Controller Module SELF...
  • Page 332 The important thing is that the address output of that access needs the correct mode programming information on the correct address bits. Figure 15-10 shows the command, which occurs in the first clock of the bus cycle. 15-18 MCF5282 User’s Manual MOTOROLA...
  • Page 333: Sdram Example

    (t ACTV Precharge command to ACTV Last data input to command (t PALL Auto-refresh period for 4096 rows (t MOTOROLA Chapter 15. Synchronous DRAM Controller Module A[31:0] D[31:0] Parameter command (t ACTV command (t SDRAM Example...
  • Page 334: Sdram Interface Configuration

    512-Kbyte block of each 1-Mbyte partition in the SDRAM (each 16 Mbytes). The starting address of the SDRAM is 0xFF88_0000. Continuous page mode feature is used. 15-20 RTIM 0000_0000_0010_0110 0026 Description value is 70 ns, indicating a 3-clock refresh-to- MCF5282 User’s Manual A10 = CMD timing. ACTV MOTOROLA...
  • Page 335: Dacr Initialization

    Setting 31–18 1111_1111_ 1000_10 17–16 — — 13–12 CASL — 10–8 — IMRS 5–4 MOTOROLA Chapter 15. Synchronous DRAM Controller Module SDRAM Component Bank 1 512 Kbyte 1 Mbyte 512 Kbyte 1111_1111_1000_10xx — — IMRS 0000_x011_x000_0000 0300 Description Base address. So DACR0[31–16] = 0xFF88, placing the starting address of the SDRAM accessible memory at 0xFF88_0000.
  • Page 336: Dmr Initialization

    Enable supervisor data accesses. Disable user code accesses. Enable user data accesses. Enable accesses. 15-22 Description Indicates precharge has not been initiated. Reserved. Don’t care. 0000_0000_0111_01xx 0 074 — xxxx_xxx0_x111_0101 0075 Figure 15-14. DMR0 Register Description MCF5282 User’s Manual — MOTOROLA...
  • Page 337: Mode Register Initialization

    Although A[31:20] corresponds to the address programmed in DACR0, according to how DACR0 and DMR0 are initialized, bit 19 must be set to hit in the SDRAM. Thus, before the mode register bit is set, DMR0[19] must be set to enable masking. MOTOROLA Chapter 15. Synchronous DRAM Controller Module SDRAM Pins...
  • Page 338: Initialization Code

    Mode Register Initialization Sequence: move.l #0x00600075, d0//Mask bit 19 of address move.l d0, DMR0 move.l #0xFF888340, d0//Enable DACR0[IMRS]; DACR0[RE] remains set move.l d0, DACR0 move.l #0x00000000, d0//Access SDRAM address to initialize mode register move.l d0, 0xFF800800 15-24 MCF5282 User’s Manual MOTOROLA...
  • Page 339 SDRAM Example MOTOROLA Chapter 15. Synchronous DRAM Controller Module 15-25...
  • Page 340 SDRAM Example 15-26 MCF5282 User’s Manual MOTOROLA...
  • Page 341: Overview

    (SARn), destination address register (DARn), byte count register (BCRn), control register (DCRn), and status register (DSRn). Transfers are dual address to on-chip devices, such as UART, SDRAM controller, and GPIOs. MOTOROLA NOTE Chapter 16. DMA Controller Module...
  • Page 342: Dma Module Features

    Channel System Bus Address Enables System Bus Size Current Master Attributes Control Arbitration/ Control Data Path Control Figure 16-1. DMA Signal Diagram NOTE MCF5282 User’s Manual Channel 3 SAR3 DAR3 Interrupts BCR3 DCR3 DSR3 Bus Interface Registered Bus Signals MOTOROLA...
  • Page 343: Dma Request Control (dmareqc)

    1001 UART1. 1010 UART2. 0100 DMA Timer 0. 0101 DMA Timer 1. 0110 DMA Timer 2. 0111 DMA Timer 3. All other values are reserved and will not generate a DMA request. MOTOROLA — 0000_0000_0000_0000 DMAC2 DMAC1 0000_0000_0000_0000 IPSBAR + 0x014 Description Chapter 16.
  • Page 344: Dma Transfer Overview

    3. Channel termination—Occurs after the operation is finished, either successfully or due to an error. The channel indicates the operation status in the channel’s DSR, described in Section 16.4.5, “DMA Status Registers (DSR0–DSR3).” 16-4 Control and Data Memory/ Peripheral Memory/ Peripheral Control and Data MCF5282 User’s Manual MOTOROLA...
  • Page 345: Dma Controller Module Programming Model

    The DMA module originally supported a left-justified 16-bit byte count register (BCR). This function was later reimplemented as a right-justified 24-bit BCR. The operation of the DMA and the interpretation of the BCR is controlled by the MPARK[BCR24BIT]. See Section 8.5.3, “Bus Master Park Register (MPARK)" for more details. MOTOROLA DMA Controller Module Programming Model [23:16] Source address register 0 (SAR0) [p.
  • Page 346: Source Address Registers (sarn)

    DARn, shown in Figure 16-5, holds the address to which the DMA controller sends data. Field Reset Address Figure 16-5. Destination Address Registers (DARn) 16-6 0000_0000_0000_0000_0000_0000_0000_0000 IPSBAR + 0x100, 0x140, 0x180, 0x1C0 NOTE “Memory Base Address NOTE 0000_0000_0000_0000_0000_0000_0000_0000 IPSBAR + 0x104, 0x144, 0x184, 0x1C4 MCF5282 User’s Manual Register MOTOROLA...
  • Page 347: Byte Count Registers (bcr0–bcr3)

    Figure 16-7 shows BCRn for BCR24BIT = 0. Field Reset Address Figure 16-7. Byte Count Registers (BCRn)—BCR24BIT = 0 DSRn[DONE], shown in Figure 16-9, is set when the block transfer is complete. MOTOROLA DMA Controller Module Programming Model NOTE NOTE 0000_0000_0000_0000_0000_0000 IPSBAR + 0x10C, 0x14C, 0x18C, 0x1CC...
  • Page 348: Dma Control Registers (dcrn)

    Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. 16-8 — — SINC 0000_0000_0000_0000 — IPSBAR + 0x108, 0x148, 0x188, 0x1C8 Description MCF5282 User’s Manual SSIZE DINC DSIZE START MOTOROLA...
  • Page 349 0 DMA inactive 1 The DMA begins the transfer in accordance to the values in the control registers. START is cleared automatically after one system clock and is always read as logic 0. MOTOROLA DMA Controller Module Programming Model Description...
  • Page 350: Dma Status Registers (dsrn)

    0 No request is pending or the channel is currently active. Cleared when the channel is selected. 1 The DMA channel has a transfer remaining and the channel is not selected. 16-10 Description — 0000_0000 IPSBAR + 0x110, 0x150, 0x190, 0x1D0 Description MCF5282 User’s Manual DONE MOTOROLA...
  • Page 351: Dma Controller Module Functional Description

    • Cycle-steal mode (DCRn[CS] = 1)—Only one complete transfer from source to destination occurs for each request. If DCRn[EEXT] is set, a request can be either internal or external. An internal request is selected by setting DCRn[START]. An MOTOROLA DMA Controller Module Functional Description Description access, Chapter 16.
  • Page 352: Data Transfer Modes

    If the BCRn is a multiple of DCRn[BWC], the DMA request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters. If a termination error occurs, DSRn[BES,DONE] are set and DMA transactions stop. 16-12 MCF5282 User’s Manual MOTOROLA...
  • Page 353: Channel Initialization And Startup

    SINC,DINC] and on the starting address. Increment values can be 1, 2, 4, or 16 for byte, word, longword, or 16-byte line transfers, respectively. If the address register is programmed to remain unchanged (no count), the register is not incremented after the data transfer. MOTOROLA DMA Controller Module Functional Description Chapter 16. DMA Controller Module 16-13...
  • Page 354: Data Transfer

    4. Repeat longwords until SARn = 0x00F0. 5. Read byte from 0x00F0—write byte, increment SARn. If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the configured size. 16-14 MCF5282 User’s Manual MOTOROLA...
  • Page 355: Termination

    The processor can read DSRn to determine whether the transfer terminated successfully or with an error. DSRn[DONE] is then written with a one to clear the interrupt and the DONE and error bits. MOTOROLA DMA Controller Module Functional Description Chapter 16. DMA Controller Module...
  • Page 356 DMA Controller Module Functional Description 16-16 MCF5282 User’s Manual MOTOROLA...
  • Page 357: Overview

    50MHz • Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of 25 MHz • Retransmission from transmit FIFO following a collision (no processor bus utilization) MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-1...
  • Page 358: Full And Half Duplex Operation

    (EMDC/EMDIO pins) to the transceiver. Refer to the MMFR and MSCR register descriptions as well as the section on the MII for a description of how to read and write registers in the transceiver via this interface. 17-2 MCF5282 User’s Manual MOTOROLA...
  • Page 359: Address Recognition Options

    Address recognition options are discussed in detail in Section 17.4.8, “Ethernet Address Recognition”. 17.2.4 Internal Loopback Internal loopback mode is selected via RCR[LOOP]. Loopback mode is discussed in detail in Section 17.4.13, “Internal and External Loopback”. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-3...
  • Page 360: Fec Top-level Functional Diagram

    • Address recognition for receive frames • Random number generation for transmit collision backoff timer 17-4 Controller RAM I/F Transmit Counters ETXEN ETXD[3:0] ETXER MCF5282 User’s Manual FIFO FEC Bus Receive ETCLK ERXCLK ERXDV ECRS,ECOL ERXD[3:0] ERXER MII/7-WIRE DATA OPTION MOTOROLA...
  • Page 361: Functional Description

    (Ethernet driver) interface for transmitting and receiving frames. Following the software initialization and operation sections are sections providing a detailed description of the functions of the FEC. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) NOTE Chapter 21, “DMA...
  • Page 362: Initialization Sequence

    Reset Value Transmission is aborted (bad CRC appended) Receive activity is aborted All DMA activity is terminated Cleared Cleared Halt operation Description Initialize EIMR Clear EIR (write 0xFFFF_FFFF) TFWR (optional) IALR / IAUR GAUR / GALR MCF5282 User’s Manual MOTOROLA...
  • Page 363: Microcontroller Initialization

    17.4.4 User Initialization (After Asserting ECR[ETHER_EN]) After asserting ECR[ETHER_EN], the user can set up the buffer/frame descriptors and write to the TDAR and RDAR. Refer to Section 17.6, “Buffer Descriptors” for more details. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Description MSCR (optional)
  • Page 364: Network Interface Options

    Collision ECOL Carrier Sense ECRS Receive Clock ERXCLK ERXDV Receive Data ERXD[3:0] Receive Error ERXER EMDC EMDIO Input/Output EMAC PIN Transmit Clock ETXCLK ETXEN Transmit Data ETXD[0] Collision ECOL Receive Clock ERXCLK ERXDV Receive Data ERXD[0] MCF5282 User’s Manual MOTOROLA...
  • Page 365: Fec Frame Transmission

    After the transmitter has stopped the GRA (graceful stop complete) interrupt is asserted. If TCR[GTS] is cleared, the FEC resumes transmission with the next frame. The Ethernet controller transmits bytes least significant bit first. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-9...
  • Page 366: Fec Frame Reception

    (RFINT bit in EIR, maskable by RFIEN bit in EIMR), indicating that a frame has been received and is in memory. The Ethernet controller then waits for a new frame. The Ethernet controller receives serial data LSB first. 17-10 MCF5282 User’s Manual MOTOROLA...
  • Page 367: Ethernet Address Recognition

    MISS bit in the receive buffer descriptor is set; otherwise, the frame will be rejected. In general, when a frame is rejected, it is flushed from the FIFO. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-11...
  • Page 368: Ethernet Address Recognition—receive Block Decisions

    Set MC bit in Rcv BD if multicast Set BC bit in Rcv BD if broadcast MCF5282 User’s Manual True Receive Frame Set MC bit in RCV BD if multicast True True Pause Frame False Reject Frame Flush from FIFO Receive Frame MOTOROLA...
  • Page 369: Hash Algorithm

    56/64 (or 87.5%) of the group address frames from reaching memory. Those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Receive Address...
  • Page 370: Destination Address To 6-bit Hash

    95:ff:ff:ff:ff:ff d5:ff:ff:ff:ff:ff f5:ff:ff:ff:ff:ff db:ff:ff:ff:ff:ff fb:ff:ff:ff:ff:ff bb:ff:ff:ff:ff:ff 8b:ff:ff:ff:ff:ff 0b:ff:ff:ff:ff:ff 3b:ff:ff:ff:ff:ff 7b:ff:ff:ff:ff:ff 5b:ff:ff:ff:ff:ff 27:ff:ff:ff:ff:ff 07:ff:ff:ff:ff:ff 57:ff:ff:ff:ff:ff 77:ff:ff:ff:ff:ff f7:ff:ff:ff:ff:ff c7:ff:ff:ff:ff:ff 97:ff:ff:ff:ff:ff a7:ff:ff:ff:ff:ff 17-14 6-bit Hash (in hex) 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 MCF5282 User’s Manual Hash Decimal Value MOTOROLA...
  • Page 371 4f:ff:ff:ff:ff:ff 1f:ff:ff:ff:ff:ff 3f:ff:ff:ff:ff:ff bf:ff:ff:ff:ff:ff 9f:ff:ff:ff:ff:ff df:ff:ff:ff:ff:ff ef:ff:ff:ff:ff:ff 93:ff:ff:ff:ff:ff b3:ff:ff:ff:ff:ff f3:ff:ff:ff:ff:ff d3:ff:ff:ff:ff:ff 53:ff:ff:ff:ff:ff 73:ff:ff:ff:ff:ff 23:ff:ff:ff:ff:ff 13:ff:ff:ff:ff:ff 3d:ff:ff:ff:ff:ff MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 6-bit Hash (in Hash Decimal hex) Value 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21...
  • Page 372: Full Duplex Flow Control

    (TCR[RFC_PAUSE]) status bit is asserted while the transmitter is paused due to reception of a pause frame. 17-16 6-bit Hash (in Hash Decimal hex) Value 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x0180_c200_0001 or Physical Address 0x8808 0x0001 0x0000 to 0xFFFF MCF5282 User’s Manual MOTOROLA...
  • Page 373: Inter-packet Gap (ipg) Time

    17.4.13 Internal and External Loopback Both internal and external loopback are supported by the Ethernet controller. In loopback mode, both of the FIFOs are used and the FEC actually operates in a full-duplex fashion. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-17...
  • Page 374: Ethernet Error-handling Procedure

    LC bit is set in the EIR register. The FEC will then continue to the next transmit buffer descriptor and begin transmitting the next frame. The “LC” interrupt will be asserted if enabled in the EIMR register. 17-18 MCF5282 User’s Manual MOTOROLA...
  • Page 375: Reception Errors

    When the receive frame length exceeds MAX_FL bytes the BABR interrupt will be generated, and the LG bit in the end of frame RxBD will be set. The frame is not truncated unless the frame length exceeds 2047 bytes). MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-19...
  • Page 376: Top Level Module Memory Map

    Name Width Interrupt Event Register EIMR Interrupt Mask Register RDAR Receive Descriptor Active Register TDAR Transmit Descriptor Active Register Ethernet Control Register MDATA MII Data Register MSCR MII Speed Control Register MIBC MIB Control/Status Register MCF5282 User’s Manual Description MOTOROLA...
  • Page 377: Mib Block Counters Memory Map

    Package objects are supported by the FEC but do not require counters in the MIB block. In addition, some of the recommended package objects which are supported do not require MIB counters. Counters for transmit and receive full duplex flow control frames are included as well. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Name Width...
  • Page 378: Mib Counters Memory Map

    Frames Transmitted with Tx FIFO Underrun Frames Transmitted with Carrier Sense Error Frames Transmitted with SQE Error Flow Control Pause frames transmitted Octet count for Frames Transmitted w/o Error RMON Rx packet count RMON Rx Broadcast Packets RMON Rx Multicast Packets MCF5282 User’s Manual MOTOROLA...
  • Page 379: Registers

    These interrupts can be divided into operational interrupts, transceiver/network error interrupts, and internal error interrupts. Interrupts which may occur in normal operation are GRA, TXF, TXB, RXF, RXB, and MII. Interrupts resulting from errors/problems detected MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Programming Model...
  • Page 380: Ethernet Interrupt Event Register (eir)

    Babbling transmit error. This bit indicates that the transmitted frame length has exceeded RCR[MAX_FL] bytes. This condition is usually caused by a frame that is too long being placed into the transmit data buffer(s). Truncation does not occur. MCF5282 User’s Manual — MOTOROLA...
  • Page 381 Bits Name EBERR 18–0 — MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Description Graceful stop complete. This interrupt will be asserted for one of three reasons. Graceful stop means that the transmitter is put into a pause state after completion of the frame currently being transmitted.
  • Page 382: Interrupt Mask Register (eimr)

    The corresponding EIR bit reflects the state of the interrupt signal even if the corresponding EIMR bit is set. 0 The corresponding interrupt source is masked. 1 The corresponding interrupt source is not masked. Reserved, should be cleared. MCF5282 User’s Manual — MOTOROLA...
  • Page 383: Receive Descriptor Active Register (rdar)

    The TDAR register is cleared at reset, when ECR[ETHER_EN] is cleared, or when ECR[RESET] is set. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) R_DES_ACTIVE 0000_0000_0000_0000 —...
  • Page 384: Transmit Descriptor Active Register (tdar)

    Reserved, should be cleared. Cleared by the FEC device whenever no additional “ready” descriptors remain in the transmit ring. Also cleared when ECR[ETHER_EN] is cleared. Reserved, should be cleared. — 1111_0000_0000_0000 — 0000_0000_0000_0000 IPSBAR + 0x1024 MCF5282 User’s Manual — ETHER_EN RESET MOTOROLA...
  • Page 385: Mii Management Frame Register (mmfr)

    Reset Field Reset Address Figure 17-9. MII Management Frame Register (MMFR) MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Description Reserved. When this bit is set, the FEC is enabled, and reception and transmission are possible. When this bit is cleared, reception is immediately stopped and transmission is stopped after a bad CRC is appended to any currently transmitted frame.
  • Page 386: Mmfr Field Descriptions

    PHY device. Turn around. This field must be programmed to 10 to generate a valid MII management frame. Management frame data. This is the field for data to be written to or read from the PHY register. MCF5282 User’s Manual MOTOROLA...
  • Page 387: Mii Speed Control Register (mscr)

    EMDC. The EMDC generated will have a 50% duty cycle except when MII_SPEED is changed during operation (change will take effect following either a rising or falling edge of EMDC). MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) —...
  • Page 388: Mib Control Register (mibc)

    A read/write control bit. If set, the MIB logic will halt and not update any MIB counters. A read-only status bit. If set the MIB block is not currently updating any MIB counters. Reserved. MCF5282 User’s Manual EMDC frequency 2.5 MHz 2.36 MHz 2.5 MHz 2.5 MHz 2.5 MHz MOTOROLA...
  • Page 389: Receive Control Register (rcr)

    Name 31–27 — 26–16 MAX_FL 15–6 — BC_REJ PROM MII_MODE MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) MAX_FL 0000_0101_1110_1110 — FCE BC_REJ PROM MII_MODE DRT LOOP 0000_0000_0000_0001 IPSBAR + 0x1084 Description Reserved, should be cleared. Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the end of the frame.
  • Page 390: Transmit Control Register (tcr)

    The system clock is substituted for the ETXCLK when LOOP is asserted. DRT must be set to zero when asserting LOOP. — 0000_0000_0000_0000 RFC_PAUSE TFC_PAUSE 0000_0000_0000_0000 IPSBAR + 0x10C4 MCF5282 User’s Manual FDEN HBC GTS MOTOROLA...
  • Page 391: Tcr Field Descriptions

    (Destination Address) field of receive frames with an individual DA. In addition, this register is used in bytes 0 through 3 of the 6-byte source address field when transmitting PAUSE frames. This register is not reset and must be initialized by the user. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Description Reserved, should be cleared.
  • Page 392: Physical Address Low Register (palr)

    Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits 7:0) of the 6-byte individual address to be used for exact match, and the Source Address field in PAUSE frames. PADDR2 Uninitialized TYPE 1000_1000_0000_1000 IPSBAR + 0x10E8 MCF5282 User’s Manual MOTOROLA...
  • Page 393: Opcode/pause Duration Register (opd)

    DA field of receive frames with an individual DA. This register is not reset and must be initialized by the user. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Description...
  • Page 394: Descriptor Individual Upper Address Register (iaur)

    The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32. IADDR2 Uninitialized IADDR2 Uninitialized IPSBAR + 0x111C MCF5282 User’s Manual MOTOROLA...
  • Page 395: Descriptor Group Upper Address Register (gaur)

    The GALR register is written by the user. This register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. This register must be initialized by the user. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Description...
  • Page 396: Descriptor Group Lower Address Register (galr)

    Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0. — 0000_0000_0000_0000 — 0000_0000_0000_0000 IPSBAR + 0x1144 MCF5282 User’s Manual X_WMRK MOTOROLA...
  • Page 397: Fifo Receive Bound Register (frbr)

    Name 31–10 — 9–2 R_BOUND 1–0 — MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Descriptions Reserved, should be cleared. Number of bytes written to transmit FIFO before transmission of a frame begins 0x 64 bytes written 10 128 bytes written 11 192 bytes written —...
  • Page 398: Fifo Receive Start Register (frsr)

    0000_0101_0000_0000 IPSBAR + 0x1150 Descriptions Reserved, read as 0 (except bit 10, which is read as 1). Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs. Reserved, read as 0. MCF5282 User’s Manual — MOTOROLA...
  • Page 399: Receive Descriptor Ring Start Register (erdsr)

    This register is not reset and must be initialized by the user prior to operation. Field Reset Field Reset Address Figure 17-25. Transmit Buffer Descriptor Ring Start Register (ETDSR) MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) R_DES_START Uninitialized R_DES_START Uninitialized IPSBAR + 0x1180 Descriptions Reserved, should be cleared.
  • Page 400: Receive Buffer Size Register (emrbr)

    Reserved, should be cleared. — Uninitialized R_BUF_SIZE Uninitialized IPSBAR + 0x11B8 Descriptions Reserved, should be written to 0 by the host processor. Receive buffer size. Reserved, should be written to 0 by the host processor. MCF5282 User’s Manual — MOTOROLA...
  • Page 401: Buffer Descriptors

    TCP header in a 2nd buffer, IP header in a 3rd buffer, Ethernet/IEEE 802.3 header in a 4th buffer. The Ethernet MAC does not prepend the Ethernet header (destination address, source address, length/type field(s)), so this must be MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-45...
  • Page 402 The frame status/length information is written into the receive FIFO following the end of the frame (as a single 32-bit word) by the receive logic. The length 17-46 MCF5282 User’s Manual MOTOROLA...
  • Page 403: Ethernet Receive Buffer Descriptor (rxbd)

    L bit is set. Offset + 0 Offset + 2 Offset + 4 Offset + 6 Figure 17-27. Receive Buffer Descriptor (RxBD) MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) — — Data Length Rx Data Buffer Pointer - A[31:16]...
  • Page 404: Receive Buffer Descriptor Field Definitions

    If this bit is set the CR bit will not be set. — Reserved. Receive CRC error. Written by the FEC. This frame contains a CRC error and is an integral number of octets in length. This bit is valid only if the L-bit is set. MCF5282 User’s Manual Description MOTOROLA...
  • Page 405: Ethernet Transmit Buffer Descriptor (txbd)

    Transmit frame status is indicated via individual interrupt bits (error conditions) and in statistic counters in the MIB block. See Section 17.5.3, “MIB Block Counters Memory Map” for more details. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Field Name Overrun. Written by the FEC. A receive FIFO overrun occurred during frame reception.
  • Page 406: Transmit Buffer Descriptor (txbd)

    1 Transmit the CRC sequence after the last data byte. Append bad CRC. Written by user (only valid if L = 1). 0 No effect 1 Transmit the CRC sequence inverted after the last data byte (regardless of TC value). — Reserved. MCF5282 User’s Manual Description MOTOROLA...
  • Page 407 BD for the frame. The driver should follow that with a write to TDAR which will trigger the FEC to poll the next BD in the ring. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Field Name Data Length Data Length, written by user.
  • Page 408 Buffer Descriptors 17-52 MCF5282 User’s Manual MOTOROLA...
  • Page 409: Low-power Mode Operation

    In doze mode with the WCR[DOZE] bit cleared, the watchdog timer continues to operate normally. Watchdog timer operation stops in stop mode. When stop mode is exited, the watchdog timer continues to operate in its pre-stop mode state. MOTOROLA Watchdog Operation Upon Watchdog reset stopped otherwise...
  • Page 410: Signals

    IPSBAR offset for base address of 0x0014_0000. 18.5.1 Memory Map Refer to Table 18-2 for an overview of the watchdog memory map. 18-2 IPBUS 16-bit WCNTR 16-bit Watchdog Counter Load Counter 16-bit WMR IPBUS MCF5282 User’s Manual 16-bit WSR Count = 0 Reset MOTOROLA...
  • Page 411: Watchdog Control Register (wcr)

    The 16-bit WCR configures watchdog timer operation. Field Reset Field Reset Address Figure 18-2. Watchdog Control Register (WCR) MOTOROLA Bits 15–8 Bits 7–0 Watchdog Control Register (WCR) Watchdog Modulus Register (WMR) Watchdog Count Register (WCNTR) Watchdog Service Register (WSR) —...
  • Page 412: Watchdog Modulus Register (wmr)

    1 Watchdog timer enabled 0 Watchdog timer disabled 18.5.2.2 Watchdog Modulus Register (WMR) Field WM15 WM14 Reset Field Reset Address Figure 18-3. Watchdog Modulus Register (WMR) 18-4 Description WM13 WM12 WM11 1111_1111 1111_1111 IPSBAR + 0x0014_0002, 0x0014_0003 MCF5282 User’s Manual WM10 MOTOROLA...
  • Page 413: Watchdog Count Register (wcntr)

    However, writing any value other than 0x5555 or 0xAAAA to WSR resets the servicing sequence, requiring both values to be written to keep the watchdog timer from causing a reset. MOTOROLA Description WC13...
  • Page 414: Watchdog Service Register (wsr)

    Memory Map and Registers Field WS15 WS14 Reset Field Reset Address Figure 18-5. Watchdog Service Register (WSR) 18-6 WS13 WS12 WS11 0000_0000 0000_0000 IPSBAR + 0x0014_0006, 0x0014_0007 MCF5282 User’s Manual WS10 MOTOROLA...
  • Page 415: Pit Block Diagram

    This device has four programmable interrupt timers, PIT0–PIT3. 19.2 Block Diagram System Clock Divide Prescaler by 2 PRE[3:0] DOZE HALTED MOTOROLA Chapter 19. Programmable Interrupt Timer Modules (PIT0–PIT3) IPBUS 16-bit PCNTR COUNT = 0 16-bit PIT Counter Load Counter 16-bit PMR IPBUS Figure 19-1.
  • Page 416: Pit Module Operation In Low-power Modes

    Any IRQx Interrupt at or above level in LPICR stopped otherwise Any IRQx Interrupt at or above level in LPICR stopped otherwise Stopped No. Any IRQx Interrupt will be serviced upon normal stopped otherwise exit from halted mode MCF5282 User’s Manual Mode Exit MOTOROLA...
  • Page 417: Programmable Interrupt Timer Modules Memory Map

    • The PIT control and status register (PCSR) configures the timer’s operation. • The PIT modulus register (PMR) determines the timer modulus reload value. • The PIT count register (PCNTR) provides visibility to the counter value. MOTOROLA Chapter 19. Programmable Interrupt Timer Modules (PIT0–PIT3) Bits 15–8...
  • Page 418: Pit Control And Status Register (pcsr)

    0000_0000 HALTED 0000_0000 Description System Clock Divisor 0000 0001 0010 0011 0100 0101 0110 0111 MCF5282 User’s Manual PRE2 PRE1 PRE0 System Clock Divisor 1000 1001 1,024 1010 2,048 1011 4,096 1100 8,192 1101 16,384 1110 32,768 1111 65,536 MOTOROLA...
  • Page 419 PIT counter. The prescaler counter is reset anytime a new value is loaded into the PIT counter and also during reset. Reading the PMR returns the value written in the modulus latch. Reset initializes PMR to 0xFFFF. MOTOROLA Chapter 19. Programmable Interrupt Timer Modules (PIT0–PIT3) Memory Map and Registers...
  • Page 420: Set-and-forget Timer Operation

    0x0000. If the PIE bit is set in PCSR, the PIF flag issues an interrupt request to the CPU. 19-6 PM13 PM12 PM11 1111_1111 1111_1111 PC13 PC12 PC11 1111_1111 1111_1111 MCF5282 User’s Manual PM10 PC10 MOTOROLA...
  • Page 421: Free-running Timer Operation

    The 16-bit PIT counter and prescaler supports different timeout periods. The prescaler divides the system clock as selected by the PRE[3:0] bits in PCSR. The PM[15:0] bits in PMR select the timeout period. Timeout period MOTOROLA Chapter 19. Programmable Interrupt Timer Modules (PIT0–PIT3) 0x0001 0x0000...
  • Page 422: Interrupt Operation

    The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR. 19-8 MCF5282 User’s Manual MOTOROLA...
  • Page 423: Features

    • Programmable prescaler • Pulse widths variable from microseconds to seconds • Single 16-bit pulse accumulator • Toggle-on-overflow feature for pulse-width modulator (PWM) generation • External timer clock input (SYNCA/SYNCB) MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) 20-1...
  • Page 424: Gpt Block Diagram

    TCRE Interrupt Interrupt Request Logic CH. 0 Capture GPTx0 LOGIC CH. 0 Compare CH. 1 Capture GPTx1 LOGIC CH. 1 Compare CH.3 Capture PA Input GPTx3 LOGIC CH. 3 Compare EDGE DETECT PAIF Divide System Divide-by-64 by 2 Clock MOTOROLA...
  • Page 425: Signal Description

    The GPTn[2:0] pins are for channel 2–0 input capture and output compare functions. These pins are available for general-purpose input/output (I/O) when not configured for timer functions. MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) Watchdog Operation Normal...
  • Page 426: Gptn3

    GPT Toggle-on-Overflow Register (GPTTOV) GPT Control Register 1 (GPTCTL1) Reserved GPT Control Register 2 (GPTCTL2) GPT Interrupt Enable Register (GPTIE) GPT System Control Register 2 (GPTSCR2) GPT Flag Register 1 (GPTFLG1) GPT Flag Register 2 (GPTFLG2) MCF5282 User’s Manual Access — — MOTOROLA...
  • Page 427: Gpt Input Capture/output Compare Select Register (gptios)

    Select Register (GPTIOS) Field Reset Address Figure 20-2. GPT Input Capture/Output Compare Select Register (GPTIOS) MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) Bits 7–0 GPT Channel 0 Register High (GPTC0H) GPT Channel 0 Register Low (GPTC0L) GPT Channel 1 Register High (GPTC1H)
  • Page 428: Gpt Compare Force Register (gpcforc)

    20.5.3 GPT Output Compare 3 Mask Register (GPTOC3M) Field Reset Address Figure 20-4. GPT Output Compare 3 Mask Register (GPTOC3M) 20-6 Description — 0000_0000 IPSBAR + 0x1A_00001, 0x1B_0001 Description NOTE — 0000_0000 IPSBAR + 0x1A_0002, 0x1B_0002 MCF5282 User’s Manual OC3M MOTOROLA...
  • Page 429: Gptoc3m Field Descriptions

    2:0 compares. For each OC3M bit that is set, the output compare action reflects the corresponding OC3D bit. 20.5.5 GPT Counter Register (GPTCNT) Field Reset Address Figure 20-6. GPT Counter Register (GPTCNT) MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) Description — 0000_0000 IPSBAR + 0x1A_0003, 0x1B_0003 Description...
  • Page 430: Gptcnt Field Descriptions

    Writing logic 1s to the flags clears them only when TFFCA is clear. 1 Fast flag clearing 0 Normal flag clearing 3–0 — Reserved, should be cleared. 20-8 Description — TFFCA 0000_0000 IPSBAR + 0x1A_0006, 0x1B_0006 Description MCF5282 User’s Manual — MOTOROLA...
  • Page 431: Fast Clear Flag Logic

    0 Toggle output compare pin on overflow feature disabled 20.5.8 GPT Control Register 1 (GPTCTL1) Field Reset Address Figure 20-10. GPT Control Register 1 (GPTCTL1) MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) Write GPTFLG1 Register Data Bit n TFFCA —...
  • Page 432: Gptcl1 Field Descriptions

    20.5.10 GPT Interrupt Enable Register (GPTIE) Field Reset Address Figure 20-12. GPT Interrupt Enable Register (GPTIE) 20-10 Description EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B 0000_0000 IPSBAR + 0x1A_000B, 0x1B_000B Description — 0000_0000 IPSBAR + 0x1A_000C, 0x1B_000C MCF5282 User’s Manual EDG0A MOTOROLA...
  • Page 433: Gptie Field Descriptions

    111 Prescaler divisor 128 Note: The newly selected prescaled clock does not take effect until the next synchronized edge of the prescaled clock when the clock count transitions to 0x0000.) MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) Description —...
  • Page 434: Gptflg1 Field Descriptions

    Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any access to the GPT counter registers clears GPT flag register 2. 20-12 — 0000_0000 IPSBAR + 0x1A_000E, 0x1B_000E Description — 0000_0000 IPSBAR + 0x1A_000F, 0x1B_000F Description MCF5282 User’s Manual MOTOROLA...
  • Page 435: Gpt Channel Registers (gptcn)

    GPTEN, is clear. PAMOD Pulse accumulator mode. Selects event counter mode or gated time accumulation mode. 1 Gated time accumulation mode 0 Event counter mode MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) CCNT 0000_0000_0000_0000 0x1B_0010, 0x1B_0012, 0x1B_0014, 0x1B_0016 Description...
  • Page 436: Pulse Accumulator Flag Register (gptpaflg)

    1 PAIF interrupt requests enabled 0 PAIF interrupt requests disabled 20.5.16 Pulse Accumulator Flag Register (GPTPAFLG) Field Reset Address Figure 20-18. Pulse Accumulator Flag Register (GPTPAFLG) 20-14 Description — 0000_0000 IPSBAR + 0x1A_0019, 0x1B_0019 MCF5282 User’s Manual PAOVF PAIF MOTOROLA...
  • Page 437: Pulse Accumulator Counter Register (gptpacnt)

    To ensure coherent reading of the PA counter, such that the counter does not increment between back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. These bits are read anytime, write anytime. MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) Description...
  • Page 438: Gpt Port Data Register (gptport)

    GPT port pins as inputs. These bits are read anytime, write anytime. 1 Corresponding pin configured as output 0 Corresponding pin configured as input 20-16 — 0000_0000 IPSBAR + 0x1A_001D, 0x1B_001D Description — — — 0000_0000 IPSBAR + 0x1A_001E, 0x1B_001E Description MCF5282 User’s Manual PORTT DDRT IC/OC — MOTOROLA...
  • Page 439: Prescaler

    The output compare 3 mask register masks the bits in the output compare 3 data register. The GPT counter reset enable bit, TCRE, enables channel 3 output compares to MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB)
  • Page 440: Pulse Accumulator

    The PA overflow flag, PAOVF, is set when the PA rolls over from 0xFFFF to 0x0000. The PA overflow interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests. The PA can operate in event counter mode even when the GPT enable bit, GPTEN, is clear. 20-18 NOTE NOTE MCF5282 User’s Manual MOTOROLA...
  • Page 441: Gated Time Accumulation Mode

    The PORTTn data direction register controls the data direction of an input capture pin. External pin conditions trigger input captures on input capture pins configured as inputs. MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) NOTE...
  • Page 442: Gpt Settings And Pin Functions

    CPU Digital input Output compare takes place but does not affect the pin because of the OMn/OLn setting Digital output Output compare takes place but does not affect the pin because of the OMn/OLn setting MOTOROLA...
  • Page 443: Gpt Interrupt Requests

    Channel 2 IC/OC Channel 1 IC/OC Channel 0 IC/OC PA overflow PA input Timer overflow MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) <> 0 OC action Output compare Pin driven by OC action OC action/ OC3Dn OC action/ OC3Dn Table 20-24.
  • Page 444: Gpt Channel Interrupts (cnf)

    TOF is set when the GPT counter rolls over from 0xFFFF to 0x0000. If the GPTSCR2[TOI] bit is also set, TOF generates an interrupt request. Clear TOF by writing a 1 to this flag. 20-22 NOTE NOTE NOTE MCF5282 User’s Manual MOTOROLA...
  • Page 445 When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any access to the GPT counter registers clears GPT flag register 2. When TOF is set, it does not inhibit future overflow events. MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) 20-23...
  • Page 446 Interrupts 20-24 MCF5282 User’s Manual MOTOROLA...
  • Page 447: Overview

    DTRRn registers, the DMA timer may be configured to assert an output signal, generate an interrupt, or initiate a DMA transfer on a particular event. Figure 21-1 is a block diagram of one of the four identical timer modules. MOTOROLA NOTE Chapter 21. DMA Timers (DTIM0–DTIM3)
  • Page 448: Key Features

    DMA Timer Counter Register (DTCNn) (contains incrementing value) DMA Timer Reference Register (DTRRn) (reference value for comparison with DTCN) DMA Timer Event Register (DTERn) (indicates capture or when DTCN = DTRRn) MCF5282 User’s Manual DMA Timer Extended Mode Mode Bits Register (DTXMRn) MOTOROLA...
  • Page 449: Capture Mode

    DMA Timer0 Mode Register (DTMR0) 0x400 0x404 0x408 0x40C DMA Timer1 Mode Register (DTMR1) 0x440 0x444 MOTOROLA Chapter 21. DMA Timers (DTIM0–DTIM3) DMA Timer Programming Model [23:16] [15:8] DMA Timer0 Extended Mode Register (DTXMR0) DMA Timer0 Reference Register (DTRR0) DMA Timer0 Capture Register (DTCR0)
  • Page 450: Dma Timer Mode Registers (dtmrn)

    DMA Timer3 Extended Mode Register (DTXMR3) DMA Timer3 Reference Register (DTRR3) DMA Timer3 Capture Register (DTCR3) DMA Timer3 Counter Register (DTCN3) 0000_0000_0000_0000 MCF5282 User’s Manual [15:8] [7:0] DMA Timer2 Event Register (DTER2) DMA Timer3 Event Register (DTER3) OM ORRI FRR MOTOROLA...
  • Page 451: Dma Timer Extended Mode Registers (dtxmrn)

    DTXMRs, shown in Figure 21-3, program DMA request and increment modes for the timers. Field DMAEN Reset Address IPSBAR + 0x402 (DTXMR0); + 0x442 (DTXMR1); + 0x482 (DTXMR2); + 0x4C2 Figure 21-3. DTXMRn Bit Definitions MOTOROLA Chapter 21. DMA Timers (DTIM0–DTIM3) Description — 0000_0000 (DTXMR3) DMA Timer Programming Model MODE16...
  • Page 452: Dma Timer Event Registers (dtern)

    REF and CAP flags via the internal DMA ACK signal. Field Reset Address IPSBAR + 0x403 (DTER0); + 0x443 (DTER1); 0x483 (DTER2); + 0x4C3 (DTER3) Figure 21-4. DTERn Bit Definitions 21-6 DTXMR n Field Descriptions Description — 0000_0000 R/W (ones clear/zeros have no effect) MCF5282 User’s Manual MOTOROLA...
  • Page 453: Dma Timer Reference Registers (dtrrn)

    DTINn cannot simultaneously function as a clocking source and as an input capture pin. Indeterminate operation will result if DTINn is set as the clock source when the input capture mode is used. MOTOROLA Chapter 21. DMA Timers (DTIM0–DTIM3) Description...
  • Page 454: Dma Timer Counters (dtcnn)

    — DTINn, the maximum value of DTINn is 1/5 of the system clock, as described in the MCF5282MCF523x Electrical Characteristics. 21-8 CAP (32-bit capture counter value) 0000_0000_0000_0000_0000_0000_0000_0000 32-bit timer counter value count 0000_0000_0000_0000_0000_0000_0000_0000 R/W (to reset) MCF5282 User’s Manual MOTOROLA...
  • Page 455: Code Example

    The simple example below uses Timer0 to count time-out loops. A time-out occurs when the reference value, 0xAFAF, is reached. timer0_ex clr.l DO clr.l D1 clr.l D2 MOTOROLA Chapter 21. DMA Timers (DTIM0–DTIM3) Using the DMA Timer Modules NOTE 21-9...
  • Page 456: Calculating Time-out Values

    256. For example, if a 66-MHz timer clock is divided by 16, DTMRn[PS] = 0x7F, and the timer is referenced at 0xFBC5 (64,453 decimal), the time-out period is as follows: Time-out period = [1/(66 x 10 21-10 ) x (16) x (127 + 1) x (64,453) = 2.00 s MCF5282 User’s Manual MOTOROLA...
  • Page 457: Module Description

    The QSPI module communicates with the integrated ColdFire CPU using internal memory mapped registers starting at IPSBAR + 0x340. See Section 22.5, “Programming Model.” A block diagram of the QSPI module is shown in Figure 22-1. MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module 22-1...
  • Page 458: Interface And Signals

    80-Byte QSPI Done QSPI Address Register Chip Select Logic Array Command Baud Rate Divide by 2 Generator Figure 22-1. QSPI Block Diagram MCF5282 User’s Manual QSPI Data Register QSPI_Din 8/16 Bit Shift Reg. Rx/Tx Data Reg. QSPI_Dout QSPI_CS[3:0] QSPI_CLK MOTOROLA...
  • Page 459: Internal Bus Interface

    QSPI wrap register (QWR): • The new queue pointer, QWR[NEWQP], points to the first command in the queue. • An internal queue pointer points to the command currently being executed. MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module Hi-Z or Actively Driven...
  • Page 460: Qspi Ram

    The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data, 16 words of receive data and 22-4 MCF5282 User’s Manual MOTOROLA...
  • Page 461: Qspi Ram Model

    QWR[CPTQP] shows which queue entries have been executed. The user can query this field to determine which locations in receive RAM contain valid data. MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module Register...
  • Page 462: Baud Rate Selection

    Baud rate is selected by writing a value from 2–255 into QMR[BAUD]. The QSPI uses a prescaler to derive the QSPI_CLK rate from the system clock divided by two. A baud rate value of zero turns off the QSPI_CLK. 22-6 MCF5282 User’s Manual MOTOROLA...
  • Page 463: Transfer Delays

    QDLYR[DTL] specifies a delay period. QCR[DT] determines whether the standard delay period (DT = 0) or the specified delay period (DT = 1) is used. The following expression is used to calculate the delay: MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module / [2 × (desired QSPI_CLK baud rate)]...
  • Page 464: Transfer Length

    QSPI clears QDLYR[SPE] and stops, unless wraparound mode is enabled. Wraparound mode is enabled by setting QWR[WREN]. The queue can wrap to pointer address 0x0, or to the address specified by QWR[NEWQP], depending on the state of QWR[WRTO]. 22-8 MCF5282 User’s Manual MOTOROLA...
  • Page 465: Qspi Registers

    There are a total of 80 bytes of memory used for transmit, receive, and control data. This memory is accessed indirectly using QAR and QDR. Registers and RAM are written and read by the CPU. MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module Table 22-3. QSPI Registers...
  • Page 466: Qspi Mode Register (qmr)

    Clock polarity. Defines the clock polarity of QSPI_CLK. 0 The inactive state value of QSPI_CLK is logic level 0. 1 The inactive state value of QSPI_CLK is logic level 1. 22-10 NOTE BITS CPOL CPHA 0000_0001_0000_0100 IPSBAR + 0x340 Description MCF5282 User’s Manual BAUD MOTOROLA...
  • Page 467: Qspi Delay Register (qdlyr)

    Figure 22-5 shows the QDLYR. Field SPE Reset Address Figure 22-5. QSPI Delay Register (QDLYR) MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module Description / [2 × (desired QSPI_CLK baud rate)] Chip selects are active low A = QDLYR[QCD]...
  • Page 468: Qspi Wrap Register (qwr)

    NEWQP Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a transfer. 22-12 Description ENDQP 0000_0000_0000_0000 IPSBAR + 0x348 Table 22-6. QWR Field Descriptions Description MCF5282 User’s Manual CPTQP NEWQP MOTOROLA...
  • Page 469: Qspi Interrupt Register (qir)

    QWR[HALT]. In wraparound mode, this bit is set every time the command pointed to by QWR[ENDQP] is completed. Writing a 1 to this bit clears it and writing 0 has no effect. MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module WCEFE ABRTE —...
  • Page 470: Qspi Data Register (qdr)

    The QDR, shown in Figure 22-9, is used to access QSPI RAM indirectly. The CPU reads and writes all data from and to the QSPI RAM through this register. Field Reset Address Figure 22-9. QSPI Data Register (QDR) 22-14 NOTE — 0000_0000_0000_0000 IPSBAR + 0x350 DATA 0000_0000_0000_0000 IPSBAR + 0x354 MCF5282 User’s Manual ADDR MOTOROLA...
  • Page 471: Command Ram Registers (qcr0–qcr15)

    11–8 map directly to QSPI_CS[3:0], respectively. If it is desired to use those bits as a chip select value, then an external demultiplexor must be connected to the QSPI_CS[3:0] pins. 7–0 — Reserved, should be cleared. MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module NOTE DSCK QSPI_CS...
  • Page 472: Programming Example

    QSPI_CLK frequency of 4.125 MHz (assuming a 66-MHz system clock). 2. Write QDLYR with the desired delays. 22-16 NOTE 0 ns 10 ns 10 ns Figure 22-11. QSPI Timing MCF5282 User’s Manual 20 ns MOTOROLA...
  • Page 473 11. Write QAR with 0x0010 to select the first receive RAM entry. 12. Read QDR to get the received data for each transfer. 13. Repeat steps 5 through 13 to do another transfer. MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module Programming Model...
  • Page 474 Programming Model 22-18 MCF5282 User’s Manual MOTOROLA...
  • Page 475: Simplified Block Diagram

    Module (SCM) Interrupt Controller Figure 23-1. Simplified Block Diagram UART0 can be clocked by the DTIN0 pin. UART1 can be clocked by the DTIN1 pin, and UART2 can be clocked by DTIN2. MOTOROLA NOTE UART Internal Channel Serial Control Logic Communications...
  • Page 476: Serial Module Overview

    • All three UARTs have DMA request capability • Parity, framing, and overrun error detection • False-start bit detection • Line-break detection and generation • Detection of breaks originating in the middle of a character • Start/end break interrupt/status 23-2 MCF5282 User’s Manual MOTOROLA...
  • Page 477: Uart Module Memory Map

    [p. 23-15] (Write) Do not access 0x238 0x278 0x2B8 (Read) Do not access (Write) UART output port bit set command registers—(UOP1n MOTOROLA [31:24] —(UMR1n) [p. 23-4], —(UCSRn) —(UACRn) [p. 23-13] ) [p. 23-15] Chapter 23. UART Modules Register Descriptions [23:16]...
  • Page 478: Uart Mode Registers 1 (umr1n)

    Address IPSBAR + 0x200 (UART0), 0x240 (UART1), 0x280 (UART2). After UMR1n is read or written, the pointer points to Figure 23-2. UART Mode Registers 1 (UMR1n) 23-4 [31:24] ) [p. 23-15] NOTE NOTE RESET MODE REGISTER POINTER 0000_0000 UMR2n. MCF5282 User’s Manual [23:16] [15:8] [7:0] — — command MOTOROLA...
  • Page 479: Umr1n Field Descriptions

    Bits per character. Select the number of data bits per character to be sent. The values shown do not include start, parity, or stop bits. 00 5 bits 01 6 bits 10 7 bits 11 8 bits MOTOROLA Description command for the channel was issued. See Section 23.3.5, “UART Parity Mode Parity Type (PT= 0) Even parity...
  • Page 480: Uart Mode Register 2 (umr2n)

    If CTS is asserted, the character is sent; if it is negated, the channel TXD remains in the high state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. 23-6 TxRTS TxCTS 0000_0000 UMR2n. Description MCF5282 User’s Manual MOTOROLA...
  • Page 481: Uart Status Registers (usrn)

    1 No stop bit was detected when the corresponding data character in the FIFO was received. The stop-bit check occurs in the middle of the first stop-bit position. FE is valid only when RxRDY = 1. MOTOROLA Description 5 Bits 6–8 Bits...
  • Page 482: Uart Clock Select Registers (ucsrn)

    To use the system clock for both, set UCSRn to 0xDD. Field Reset Address IPSBAR + 0x204 (UCSR0), 0x244 (UCSR1), 0x284 (UCSR2) Figure 23-5. UART Clock Select Register (UCSRn) Table 23-5 describes UCSRn fields. 23-8 Description RESET ERROR STATUS 0000_0000 Write only MCF5282 User’s Manual command in UCRn. MOTOROLA...