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Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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Enhanced Multiply-Accumulate Unit (EMAC) ColdFire Flash Module (CFM) System Control Module (SCM) Interrupt Controller Modules Edge Port Module (EPORT) External Interface Module (EIM) Synchronous DRAM Controller Module Fast Ethernet Controller (FEC) Programmable Interrupt Timer (PIT) Modules General Purpose Timer (GPT) Modules Queued Serial Peripheral Interface Module (QSPI) General Purpose I/O Module Chip Configuration Module (CCM)
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Overview ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache Static RAM (SRAM) ColdFire Flash Module (CFM) Power Management System Control Module (SCM) Clock Module Interrupt Controller Modules Edge Port Module (EPORT) Chip Select Module External Interface Module (EIM) Signal Descriptions Synchronous DRAM Controller Module DMA Controller Module Fast Ethernet Controller (FEC) Watchdog Timer Module...
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Bus Master Park Register (MPARK)... 8-12 System Access Control Unit (SACU)... 8-14 8.6.1 Overview... 8-14 8.6.2 Features... 8-14 8.6.3 Memory Map/Register Definition ... 8-15 viii CONTENTS Title Chapter 7 Power Management Chapter 8 System Control Module (SCM) MCF5282 User’s Manual Page Number MOTOROLA...
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Interrupt Control Register (ICRnx, (x = 1, 2,..., 63))... 10-11 10.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK). 10-15 10.4 Prioritization Between Interrupt Controllers ... 10-16 10.5 Low-Power Wakeup Operation ... 10-17 MOTOROLA CONTENTS Title Chapter 9 Clock Module Chapter 10 Interrupt Controller Modules...
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25-11 Free Running Timer (TIMER)... 25-26 25-12 Rx Mask Registers (RXGMASK, RX14MASK, and RX15MASK) ... 25-27 25-13 FlexCAN Error and Status Register (ESTAT) ... 25-28 25-14 Interrupt Mask Register (IMASK)... 25-30 xxviii ILLUSTRATIONS Title MCF5282 User’s Manual Page Number MOTOROLA...
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QADC Port QA Data Direction Register (DDRQA)... 27-11 27-7 Port QB Data Direction Register (DDRQB)... 27-11 27-8 QADC Control Register 0 (QACR0)... 27-12 27-9 QADC Control Register 1 (QACR1)... 27-14 27-10 QADC Control Register 2 (QACR2)... 27-17 MOTOROLA ILLUSTRATIONS Title Illustrations Page Number xxix...
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Star-Ground at the Point of Power Supply Origin ... 27-68 27-50 Input Signal Subjected to Negative Stress ... 27-69 27-51 Input Signal Subjected to Positive Stress ... 27-70 27-52 External Multiplexing of Analog Signal Sources ... 27-72 ILLUSTRATIONS Title MCF5282 User’s Manual Page Number MOTOROLA...
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33-17 Test Access Port Timing... 33-26 33-18 TRST Timing ... 33-26 33-19 BKPT Timing ... 33-27 33-20 Real-Time Trace AC Timing ... 33-28 33-21 BDM Serial Port AC Timing ... 33-28 xxxii ILLUSTRATIONS Title MCF5282 User’s Manual Page Number MOTOROLA...
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ACR Field Descriptions... 4-11 SRAM Base Address Register ... 5-2 Typical RAMBAR Setting Examples... 5-4 CFM Configuration Field ... 6-5 FLASHBAR Field Descriptions ... 6-7 CFM Register Address Map ... 6-8 CFMCR Field Descriptions ... 6-9 MOTOROLA TABLES Title Tables Page Number xxxiii...
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Clock Out and Clock In Relationships ... 9-11 Charge Pump Current and MFD in Normal Mode Operation ... 9-13 Loss of Clock Summary ... 9-16 9-10 Stop Mode Operation... 9-17 10-1 Interrupt Priority Within a Level ... 10-3 xxxiv TABLES Title MCF5282 User’s Manual Page Number MOTOROLA...
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Default Signal Functions After System Reset (External Boot Mode) ... 14-17 14-6 Transfer Size Encoding... 14-20 14-7 Processor Status Encoding... 14-32 15-1 SDRAM Commands ... 15-3 15-2 Synchronous DRAM Signal Connections ... 15-4 MOTOROLA TABLES Title Tables Page Number xxxv...
To locate any published errata or updates for this document, refer to the world-wide web at http://www.motorola.com/coldfire. Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products with the MCF5282.
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Access (DMA) controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail. xliv MCF5282 User’s Manual MOTOROLA...
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QADC module implemented on the MCF5282. • Chapter 28, “Reset Controller Module,” describes the operation of the reset controller module, detailing the different types of reset that can occur. MOTOROLA C module, including I C programming model registers. It also...
The following documentation provides useful information about the ColdFire architecture and computer architecture in general: • ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) • Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield • Computer Architecture: A Quantitative Approach, Second Edition, by John L.
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— ColdFire MCF5407 User’s Manual (MCF5407UM/AD) Additional literature on ColdFire implementations is being released as new processors become available. For a current list of ColdFire documentation, refer to the World Wide Web at http://www.motorola.com/ColdFire/. Conventions This document uses the following notational conventions: MNEMONICS In text, instruction mnemonics are shown in uppercase.
Multiply accumulate unit, also Media access controller MBAR Memory base address register Most-significant byte Most-significant bit Multiplex No operation Operand execution pipeline Program counter PCLK Processor clock PLIC Physical layer interface controller Phase-locked loop xlviii Meaning MCF5282 User’s Manual MOTOROLA...
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Any address or data register Destination register w (used for MAC instructions only) Ry,Rx Any source and destination registers, respectively Index register i (can be an address or data register: Ai, Di) MOTOROLA Meaning Table ii. Notational Conventions Operand Syntax Opcode Wildcard...
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Signal displacement value, n bits wide (example: d16 is a 16-bit displacement) Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations) Arithmetic addition or postincrement indicator – Arithmetic subtraction or predecrement indicator Arithmetic multiplication Operand Syntax Register Names Port Name Miscellaneous Operands Operations MCF5282 User’s Manual MOTOROLA...
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Least significant bit (example: lsb of D0) Least significant byte Least significant word Most significant bit Most significant byte Most significant word Carry Negative Overflow Extend Zero MOTOROLA Operand Syntax Subfields and Qualifiers is a 16-bit displacement) Condition Code Register Bit Names About This Book...
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4. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.” MOTOROLA Table iii. Revision History Substantive Changes ÷...
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0–6.” Changed CSCRn to reflect that AA is set at reset. Removed final paragraph. The paragraph incorrectly states that the MCF5282 does not have a bus monitor. MOTOROLA Table iii. Revision History Substantive Changes About This Book Section/Page...
— 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA, FEC) with standby power supply support — 512 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses (256 Kbytes on the MCF5281) – This product incorporates SuperFlash® technology licensed from SST. MOTOROLA Chapter 1. Overview...
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— Media-independent interface (MII) to transceiver (PHY) • FlexCAN 2.0B Module — Includes all existing features of the Motorola TOUCAN module — Full implementation of the CAN protocol specification version 2.0B – Standard data and remote frames (up to 109 bits long) –...
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— Two conversion command queues with a total of 64 entries — Sub-queues possible using pause mechanism — Queue complete and pause software interrupts available on both queues — Queue pointers indicate current location for each queue MOTOROLA C bus Chapter 1. Overview MCF5282 Key Features...
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— One dual-mode pulse accumulation channel per timer • Four periodic interrupt timers (PITs) — 16-bit counter — Selectable as free running or count down • Software watchdog timer — 16-bit counter — Low-power mode support MCF5282 User’s Manual MOTOROLA...
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— SDRAM controller supports 8-, 16-, and 32-bit wide memory devices — Glueless interface to SRAM devices with or without byte strobe inputs — Programmable wait state generator — 32-bit bidirectional data bus — 24-bit address bus MOTOROLA Chapter 1. Overview MCF5282 Key Features...
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— Up to 142 bits of general purpose I/O — Coherent 32-bit control — Bit manipulation supported via set/clear functions — Unused peripheral pins may be used as extra GPIO • JTAG support for system-level board testing MCF5282 User’s Manual MOTOROLA...
16-byte line-sized fetch. The cache module includes a 16-byte line fill buffer used Table 1-1. Cache Configuration Tag Address Data Array Address [10:4] [10:4] 0, [9:4] 1, [9:4] MCF5282 User’s Manual [10:2] [10:2] 0, [9:2] 1, [9:2] MOTOROLA...
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It also provides a read datapath for non-core masters (for example, DMA). 1.1.1.4 Debug Module The ColdFire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator development tools. Through a standard MOTOROLA NOTE Chapter 1. Overview MCF5282 Key Features...
This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The debug interface is a superset of the BDM interface provided on Motorola’s 683xx family of parts.
JEDEC-compliant SDRAM devices. SRAS/SCAS address multiplexing is software configurable for different page sizes. To maintain refresh capability without conflicting with concurrent accesses on the address and data buses, SRAS, SCAS, DRAMW, SDRAM_CS[1:0], and SCKE are dedicated SDRAM signals. MOTOROLA Chapter 1. Overview MCF5282 Key Features 1-11...
• Each channel programmable to normal (full-duplex), automatic echo, local loop-back, or remote loop-back mode • Automatic wake-up mode for multidrop applications • Four maskable interrupt conditions • All three UARTs have DMA request capability 1-12 MCF5282 User’s Manual MOTOROLA...
The four periodic interrupt timers (PIT0, PIT1, PIT2, PIT3) are 16-bit timers that provide precise interrupts at regular intervals with minimal processor intervention. Each timer can either count down from the value written in its PIT modulus register, or it can be a free-running down-counter. MOTOROLA Chapter 1. Overview MCF5282 Key Features 1-13...
External reset on the RSTO pin is software-assertable independent of chip reset state. There are also software-readable status flags indicating the cause of the last reset, and LVD control and status bits for setup and use of LVD reset or interrupt. 1-14 MCF5282 User’s Manual MOTOROLA...
(DAC) resistor-capacitor array and a high-gain comparator. The digital control section contains queue control logic to sequence the conversion process and interrupt generation logic. Also included are the periodic/interval timer, control and MOTOROLA Chapter 1. Overview MCF5282-Specific Features 1-15...
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MCF5282-Specific Features status registers, the 64-entry conversion command word (CCW) table, and the 64-entry result table. 1-16 MCF5282 User’s Manual MOTOROLA...
Figure 2-2 illustrates the user programming model. The model is the same as the M68000 family microprocessors, consisting of the following registers: • 16 general-purpose 32-bit registers (D0–D7, A0–A7) • 32-bit program counter (PC) • 8-bit condition code register (CCR) MCF5282 User’s Manual MOTOROLA...
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PC or places a new value in the PC, as appropriate. For some addressing modes, the PC is used as a base address for PC-relative operand addressing. MOTOROLA Chapter 2. ColdFire Core Processor Register Description...
Set to the value of the C bit for arithmetic operations; otherwise not affected. Description MCF5282 User’s Manual DATA REGISTERS ADDRESS REGISTERS USERSTACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER MOTOROLA...
Supervisor/user state. Denotes whether the processor is in supervisor mode (S = 1) or user mode (S = 0). MCF5282 User’s Manual STATUS SUPERVISOR A7 STACK POINTER VECTOR BASE REGISTER CACHE CONTROL ACCESS CONTROL ACCESS CONTROL FLASH BASE ADDRESS REGISTER RAM BASE ADDRESS REGISTER MOTOROLA...
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Ay, USP; move to USP move.l USP, Ax; move from USP These instructions are described in the ColdFire Family Programmer’s Reference Manual. MOTOROLA Description Master/interrupt state. This bit is cleared by an interrupt exception, and can be set by software during execution of the RTE or move to SR instructions.
MOVEC instruction. Table 2-3. ColdFire CPU Registers Name CPU Space (Rc) CACR 0x002 ACR0, ACR1 0x004-0x005 Written with MOVEC Memory Management Control Registers Cache control register Access control registers 0 and 1 Processor General-Purpose Registers MCF5282 User’s Manual Register Name MOTOROLA...
Table 2-4 summarizes the new instructions added to Revision A+ ISA. For more details see Section 2.14, “ColdFire Instruction Set Architecture Enhancements.” MOTOROLA Additions to the Instruction Set Architecture Written with MOVEC...
(IACK) bus cycle to obtain the vector number from the interrupt controller. The IACK cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address. 2-10 Description MCF5282 User’s Manual MOTOROLA...
All ColdFire processors support a 1024-byte vector table aligned on any 1 Mbyte address boundary (see Table 2-5). The table contains 256 exception vectors; the first 64 are defined by Motorola and the remaining 192 are user-defined interrupt vectors. Table 2-5. Exception Vector Assignments...
Counter Next User-defined interrupts FS[3:2] VECTOR[7:0] FS[1:0] PROGRAM COUNTER[31:0] SSP @ 1st Instruction of Handler Original SSP - 8 Original SSP - 9 Original SSP - 10 Original SSP - 11 MCF5282 User’s Manual Assignment STATUS REGISTER Format Field MOTOROLA...
An value. In addition, if an access error occurs during the execution of a MOVEM instruction loading from memory, any registers already updated before the fault occurs contain the operands from memory. MOTOROLA Definition Reserved Error on instruction fetch...
T-bit in the status register (SR[15] = 1), the completion of an instruction execution (for all but the STOP instruction) signals a trace exception. This functionality allows a debugger to monitor program execution. 2-14 development, ColdFire MCF5282 User’s Manual processors provide MOTOROLA...
This special type of program interrupt is discussed in detail in Chapter 29, “Debug Support.” This exception is generated in response to a hardware breakpoint register trigger. The processor does not generate an IACK cycle but rather calculates the vector number internally (vector number 12). MOTOROLA Chapter 2. ColdFire Core Processor Exceptions 2-15...
Reset also aborts any processing in progress when the reset input is recognized. Processing cannot be recovered. 2-16 MCF5282 User’s Manual MOTOROLA...
Information loaded into D0 defines the processor hardware configuration as shown in Figure 2-8. Field Reset Field MAC DIV EMAC FPU MMU Reset Figure 2-8. D0 Hardware Configuration Info MOTOROLA NOTE 1100_1111_0010_0000 — 0110_0000_1000_0000 Chapter 2. ColdFire Core Processor Exceptions DEBUG...
0000 DEBUG_A (This is the value used for MCF5282) 0001 DEBUG_B 0010 DEBUG_C 0011 DEBUG_D 0100 DEBUG_E 0x5-0xF Reserved. Information loaded into D1 defines the local memory hardware configuration as shown in Figure 2-9. 2-18 Description MCF5282 User’s Manual MOTOROLA...
1. The operand execution pipeline (OEP) is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP does not wait for the instruction fetch pipeline (IFP) to supply opwords and/or extension words. MOTOROLA Description Chapter 2. ColdFire Core Instruction Execution Timing...
The nomenclature “xxx.wl” refers to both forms of absolute addressing, xxx.w and xxx.l. 2-22 Kbus Additional Size Operations C(R/W) Word Byte, Byte 2(1/0) if read 1(0/1) if write Long Byte, Word, Byte 3(2/0) if read 2(0/2) if write Long Word, Word 2(1/0) if read 1(0/1) if write MCF5282 User’s Manual MOTOROLA...
Raccext23,<ea>x 1(0/0) Effective address of (d16,PC) not supported Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional rounding is performed (MACSR[7:4] = 1---, -11-, --11) MOTOROLA Effective Address (An) (An)+ -(An) (d16,An) 6(1/0)
Forward Backward Taken Not Taken Taken 2(0/0) — 2(0/0) 3(0/0) 1(0/0) 2(0/0) MCF5282 User’s Manual (d8,An,Xi*SF) xxx.wl #xxx (d8,PC,Xi*SF) — — — 4(0/0) 3(0/0) — 4(0/1) 3(0/1) — — — — — — — Backward Not Taken — 3(0/0) MOTOROLA...
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Not affected Instruction Field: • Register field—Specifies the destination data register, Dx. BITREV Opcode present MOTOROLA ColdFire Instruction Set Architecture Enhancements Bit Reverse Register (Supported Starting with ISA A+) V2, V3 Core (ISA_A) V4 Core (ISA_B) Chapter 2. ColdFire Core...
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(Supported Starting with ISA A+) new Dx[31:24] = old Dx[7:0] new Dx[23:16] = old Dx[15:8] new Dx[15:8] = old Dx[23:16] new Dx[7:0] = old Dx[31:24] V2, V3 Core (ISA_A) V4 Core (ISA_B) MCF5282 User’s Manual BYTEREV Register, Dx V2 Core (ISA_A+) MOTOROLA...
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— Codes: Instruction Field: • Destination Register field—Specifies the destination data register, Dx. Opcode present MOTOROLA ColdFire Instruction Set Architecture Enhancements Find First One in Register (Supported Starting with ISA A+) Old Dx[31:0] New Dx[31:0] 0b1---- . . . ---- 0x0000 0000 0b01--- .
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Z Set to the value of bit 2 of the immediate operand V Set to the value of bit 1 of the immediate operand C Set to the value of bit 0 of the immediate operand V2, V3 Core (ISA_A) V4 Core (ISA_B) MCF5282 User’s Manual STRLDSR V2 Core (ISA_A+) MOTOROLA...
EMAC improvements target three primary areas: • Improved performance of 32x32 multiply operations. • Addition of three more accumulators to minimize MAC pipeline stalls caused by exchanges between the accumulator and the pipeline’s general-purpose registers. MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC)
DSP operations. Consider a typical filtering operation where the filter is defined as in Figure 3-2. Operand Y Operand X Shift 0,1,-1 + / - Accumulator(s) MCF5282 User’s Manual MOTOROLA...
For fractional operands, the entire 64-bit product is calculated and either truncated or rounded to the most-significant 40-bit result using the round-to-nearest (even) method before it is combined with the destination accumulator. MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) –...
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The programming model includes a 16-bit mask register (MASK), which can optionally be used to generate an operand address during MAC + MOVE instructions. The application of this register with auto-increment addressing mode supports efficient implementation of circular data queues for memory operands. MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) General Operation...
3–0 Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC, MSAC, and load operations; it is not affected by MULS and MULU instructions. MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) Description...
No round on accumulator stores Signed, fractional Round on MAC.L and MSAC.L Round-to-32-bits on accumulator stores Unsigned, integer Signed, fractional Truncate on MAC.L and MSAC.L Round-to-16-bits on accumulator stores Signed, fractional Round on MAC.L and MSAC.L Round-to-16-bits on accumulator stores MCF5282 User’s Manual MOTOROLA...
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} macState; MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) /* R0.L = 0x8000 */ then Result = R0.U else Result = R0.U + 1 Memory Map/Register Set...
; move the state to memory ; restore the state from memory ; disable rounding in the macsr ; restore the accumulators ; restore the accumulator extensions ; restore the address mask ; restore the macsr MCF5282 User’s Manual MOTOROLA...
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For auto-addressing modes of post-increment and pre-decrement, the calculation of the updated An value is also shown. Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular queue implementations. MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) Memory Map/Register Set 3-11...
Loads the accumulator 0,1 extension bytes with a 32-bit operand Loads the accumulator 2,3 extension bytes with a 32-bit operand Writes the contents of accumulator 0,1 extension bytes into a CPU register Writes the contents of accumulator 2,3 extension bytes into a CPU register MCF5282 User’s Manual Description MOTOROLA...
• Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit. The remaining bits signify the first N-1 bits after the binary point. Given an N-bit number, a MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) Three-cycle...
If the EMAC is in fractional mode (MACSR[F/I] is set), SF is ignored and no shift is performed. Because a product can overflow, the following guidelines are implemented: 3-14 – ∑ ⋅ – – MCF5282 User’s Manual – ⋅ (N-1) MOTOROLA...
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((product[63:39] != 0x0000_00_0) && (product[63:39] != 0xffff_ff_1)) then { MACSR.PAVx = 1 MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) MOTOROLA Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC) /* product overflow */ then if (product[63] == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 else if (MACSR.OMC == 1)
[10:2] addressing the storage array. For the split cache configuration, the cache tag and storage arrays are accessed in parallel. The msb of the tag array address is set for instruction fetches and cleared for operand fetches; fetch address bits [9:4] provide the rest of the tag MOTOROLA Chapter 4. Cache...
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Thus, the cache or the SRAM module can service subsequent requests while the remainder of the line is being fetched and loaded into the fill buffer. MCF5282 User’s Manual MOTOROLA...
In this case, data accessed from the cache is simply discarded and no external memory references are generated. If the address is not mapped into the SRAM space, the cache handles the request in the normal fashion. MOTOROLA Buffer I or D Line...
CACR[CPDI] is cleared. For the split data/instruction cache configuration, software directly controls bit 10 which selects whether an instruction cache or data cache line is being accessed. These invalidation operations can be initiated from the ColdFire core or the debug module. MCF5282 User’s Manual MOTOROLA...
All instruction fetches are word or longword in size, and not loaded into the line-fill buffer Noncacheable Instruction fetch size is defined by Table 4-1 and loaded into the line-fill buffer, but are never written into the memory array. MCF5282 User’s Manual Description MOTOROLA...
The CACR is a 32-bit write-only supervisor control register. It is accessed in the CPU address space via the MOVEC instruction with an Rc encoding of 0x002. The CACR can be read when in background debug mode (BDM). At system reset, the entire register is cleared. MOTOROLA Width Description Cache Control Register...
1 Disable instruction caching Table 4-5 describes cache configuration and Table 4-6 describes how to set the cache invalidate all bit. — CINV DIDI DISD 0000_0000_0000_0000 CEIB DCM DBWE — 0000_0000_0000_0000 Description MCF5282 User’s Manual INVI INVD — DWP EUSP — CLNF MOTOROLA...
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Enable user stack pointer. See Section 2.2.3.2, “Supervisor/User Stack Pointers (A7 and OTHER_A7)" for more information on the dual stack pointer implementation. 0 Disable the processor’s use of the User Stack Pointer 1 Enable the processor’s use of the User Stack Pointer MOTOROLA Description Chapter 4. Cache Cache Programming Model...
Invalidate only 1 KByte data cache Data Cache Split Instruction Invalidate only 1 KByte instruction cache Data Cache Split Instruction/ No invalidate Data Cache Instruction Cache Invalidate 2 KByte instruction cache Data Cache Invalidate 2 KByte data cache MCF5282 User’s Manual Description Operation MOTOROLA...
Enable. The EN bit defines the ACR enable. Hardware reset clears this bit, disabling the ACR. 0 ACR disabled 1 ACR enabled MOTOROLA Longword Address Bits Line Line...
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WP bit, an access error terminates any attempted write with this bit set. 0 Read and write accesses permitted 1 Only read accesses permitted 1–0 — Reserved, should be cleared. 4-12 Description MCF5282 User’s Manual MOTOROLA...
See Chapter 5, “System Control Module (SCM)” for more information. SRAM Programming Model The SRAM programming model includes a description of the SRAM base address register (RAMBAR), SRAM initialization, and power management. MOTOROLA Chapter 5. Static RAM (SRAM)
DMA or CPU has priority in lower 32k bank of memory. If bit is set, DMA has priority. If bit is reset, CPU has priority. Priority is determined according to the following table. NOTE: The Motorola-recommended setting for the priority bits is 00. Undefined PRI1 PRI2 SPV —...
3. After the data has been loaded into the SRAM, it may be appropriate to load a revised value into the RAMBAR with a new set of attributes. These attributes consist of the write-protect and address space mask fields. MOTOROLA Description Chapter 5. Static RAM (SRAM)
• Concurrent verify, program, and erase of all array blocks • Read-while-write capability • Optional interrupt on command completion • Flexible scheme for protection against accidental program or erase operations • Access restriction controls for both supervisor/user and data/program space operations MOTOROLA NOTE Chapter 6. ColdFire Flash Module (CFM)
256 Kbytes of Flash space. Therefore, it takes two mass erase operations, one on mass erase block 0 and one on mass erase block 1, to erase the full 512K CFM Flash on the MCF5282. ) used for all module operations NOTE NOTE MCF5282 User’s Manual MOTOROLA...
FLASHBAR, and return zeroes when read from the debug module. • The back door enable bit, FLASHBAR[BDE], is cleared at reset, disabling back door access to the Flash. MOTOROLA Chapter 6. ColdFire Flash Module (CFM) Size Back door comparison key Flash program/erase sector protection Blocks 0H/0L (see Section 6.3.4.4, “CFM Protection Register (CFMPROT)”)
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Flash is secured. If it is the part will always boot from internal Flash, since it will be marked as valid, regardless of what is done for chip configuration. NOTE NOTE NOTE MCF5282 User’s Manual MOTOROLA...
31–19 BA[31:18] 18–9 — 7–6 — 5–1 C/I, SC, SD, UC, MOTOROLA Chapter 6. ColdFire Flash Module (CFM) 0000_0000_0000_0000 — 0000_0001_0010_000 CPU + 0xC04 Description Base address field. Defines the 0-modulo-512K base address of the Flash module. By programming this field, the Flash may be located on any 512Kbyte boundary within the processor’s four gigabyte address space.
Figure 6-5. CFM Clock Divider Register (CFMCLKD) All bits in CFMCLKD are readable. Bit 7 is a read-only status bit, while bits 6–0 can only be written once. MOTOROLA Chapter 6. ColdFire Flash Module (CFM) Description Reserved, should be cleared.
Note: The SECSTAT bit reset value is determined by the security state of the Flash. All other bits in the register are loaded at reset from the Flash Security longword stored at the array base address + 0x0000_0414. Figure 6-6. CFM Security Register (CFMSEC) 6-10 Description divider. NOTE NOTE NOTE — See Note See Note IPSBAR + 0x1D_0008 MCF5282 User’s Manual MOTOROLA...
15–0 SEC[15:0] Security field. The SEC bits define the security state of the device; see below. The security features of the CFM are described in Section 6.5, “Flash Security Operation.” MOTOROLA Chapter 6. ColdFire Flash Module (CFM) Description SEC[15:0] 0x4AC8...
The CFMPROT controls the protection of thirty-two 16-Kbyte Flash logical sectors in the 512-Kbyte Flash array. Figure 6-8 shows the association between each bit in the CFMPROT and its corresponding logical sector. 6-12 PROT See Note PROT See Note IPSBAR + 0x1D_0010 Description MCF5282 User’s Manual MOTOROLA...
Note: The CFMPROT register is loaded at reset from the Flash Supervisor/user Space Restrictions longword stored at the array base address + 0x0000_040C. Figure 6-9. CFM Supervisor Access Register (CFMSACC) MOTOROLA Chapter 6. ColdFire Flash Module (CFM) SECTOR 31 •...
1 Logical sector is mapped in data address space. 0 Logical sector is mapped in data and program address space 6-14 Description DATA See Note DATA See Note IPSBAR + 0x1D_0018 Description MCF5282 User’s Manual MOTOROLA...
See Section 6.4.3.4, “Flash User Mode Illegal Operations,” for details on what sets the ACCERR flag. 1 Access error has occurred 0 No failure — Reserved, should be cleared. MOTOROLA Chapter 6. ColdFire Flash Module (CFM) CCIF PVIOL ACCERR — 1100_0000...
Buffer empty and command completion are indicated by flags in the CFM user status register. Interrupts will be requested if enabled. MOTOROLA Chapter 6. ColdFire Flash Module (CFM) CFM Operation...
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400 kHz x (1 + (1 x 7)) 2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7)) 66 MHz 2 x (20 + 1) x (1 + (1 x 7)) MCF5282 User’s Manual = 20 = 196.43 kHz to 196.43 kHz which is MOTOROLA...
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Flash state machine sets the CCIF flag. The CBEIF flag is also set again, indicating that the address, data, and command buffers are ready for a new command sequence to begin. MOTOROLA Chapter 6. ColdFire Flash Module (CFM) WARNING is less than 150 kHz.
PROTECT bits are set for that block. Verify that the two 1024-byte pages are erased. If both pages are erased, the BLANK bit will be set in the CFMUSTAT register upon command completion. MCF5282 User’s Manual MOTOROLA...
1. The command in progress aborts 2. The Flash high voltage circuitry switches off and any pending command (CBEIF = 0) does not executed when the MCU exits stop mode. 6-22 MCF5282 User’s Manual MOTOROLA...
The CFM may be unsecured via one of two methods: 1. Executing a back door access scheme. 2. Passing an erase verify check. MOTOROLA Chapter 6. ColdFire Flash Module (CFM) NOTE WARNING...
The CFM array is not accessible for any operations via the address and data buses during reset. If a reset occurs while any command is in progress that command will immediately abort. The state of any longword being programmed or any erase pages/physical blocks being erased is not guaranteed. 6-24 NOTE MCF5282 User’s Manual MOTOROLA...
Programming Model The PMM programming model consists of one register: • The low-power control register (LPCR) specifies the low-power mode entered when the STOP instruction is issued, and controls clock activity in this low-power mode. MOTOROLA Chapter 7. Power Management...
XLPM_IPL[2:0] Exit low-power mode interrupt priority level. This field defines the interrupt priority level needed to exit the low-power mode.Refer to Table 7-3. 3–0 — Reserved, should be cleared. MOTOROLA NOTE XLPM_IPL[2:0] IPSBAR + 0x012 Description Chapter 7. Power Management Memory Map and Registers —...
This bit has no effect if the RCR[LVDE] bit is a logic 0. 1 VREG Pseudo-Standby mode (LVD enabled on power down request). 0 VREG Standby mode (LVD disabled on power down request). Reserved, should be cleared. MCF5282 User’s Manual — LVDSE — MOTOROLA...
A wakeup event is required to exit a low-power mode and return to run mode. Wakeup events consist of any of these conditions: • Any type of reset • Any valid, enabled interrupt request MOTOROLA Table 7-5. Low-Power Modes LPMD[1:0] Mode...
Stop mode must be entered in a controlled manner to ensure that any current operation is properly terminated. When exiting stop mode, most peripherals retain their pre-stop status and resume operation. The following subsections specify the operation of each module while in and when exiting low-power modes. MCF5282 User’s Manual MOTOROLA...
This system setup must meet the conditions specified in Section 7.3.1, “Low-Power Modes” for the core Watchdog interrupt to bring the part out of low-power mode. MOTOROLA NOTE Chapter 7. Power Management Functional Description...
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In wait and doze modes, the UART may generate an interrupt to exit the low-power modes. • Clearing the transmit enable bit (TE) or the receiver enable bit (RE) disables UART functions. • The UARTs are unaffected by wait mode and may generate an interrupt to exit this mode. NOTE MCF5282 User’s Manual MOTOROLA...
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In reference compare mode, where the output reference request interrupt enable (ORRI) bit of DTMR is set and the DTXMR[DMAEN] bit is cleared, an interrupt is issued when the timer counter reaches the reference value. MOTOROLA C resumes operation unless stop mode was Chapter 7. Power Management...
In stop mode, the RSTI pin synchronization is disabled and asserting the external RSTI pin will asynchronously generate an internal reset and exit any low-power modes. Registers will lose current values and must be reconfigured from reset state if needed. 7-10 MCF5282 User’s Manual MOTOROLA...
During wakeup from stop mode, the Flash clock will always clock through 16 cycles before the system clocks are enabled. This allows the Flash module time to recover from the low-power mode. Thus, software may immediately continue to fetch instructions from the Flash memory. MOTOROLA Chapter 7. Power Management 7-11...
(or clearing the QSTOP bit), returns the QADC to operation from the state prior to stop mode entry, but any conversions in progress are undefined and the QADC requires recovery time to stabilize the analog circuits before new conversions can be performed. 7-12 MCF5282 User’s Manual MOTOROLA...
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Exiting stop mode is done in one of the following ways: • Reset the FlexCAN (either by hard reset or by asserting the SOFT_RST bit in MCR). • Clearing the STOP bit in the MCR. MOTOROLA Chapter 7. Power Management Functional Description...
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FlexCAN's wake-up upon recessive to dominant edge may not conform to the standard CAN protocol, in the sense that the FlexCAN synchronization is shifted one time quanta from the required timing. This shift 7-14 MCF5282 User’s Manual MOTOROLA...
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MCU enters stop mode with a command in progress. Active commands are immediately aborted when the MCU enters stop mode. Do not execute the STOP instruction during program and erase operations. MOTOROLA NOTE Chapter 7. Power Management Functional Description 7-15...
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The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-power mode. Upon exit from halt mode, the previous low-power mode will be re-entered and changes made in halt mode will remain in effect. MOTOROLA Peripheral Status...
The SCM includes these distinctive features: • IPS base address register (IPSBAR) — Base address location for 1-Gbyte peripheral space — User control bits • Processor-local memory base address register (RAMBAR) • System control registers MOTOROLA Chapter 8. System Control Module (SCM)
5. Chip Selects This is the list of memory access priorities when viewed from the processor core. See Figure 8-1 and Table 8-2 for descriptions of the bits in IPSBAR. MOTOROLA Chapter 8. System Control Module (SCM) NOTE NOTE Register Descriptions...
CPU space address 0xC05, and another located in the SCM at IPSBAR + 0x008. ColdFire core accesses to this memory are controlled by the processor-local copy of the RAMBAR, while module accesses are enabled by the SCM's RAMBAR. — — — — IPSBAR + 0x000 Description MCF5282 User’s Manual MOTOROLA...
RAMBAR located in the processor’s CPU space must be initialized with the valid bit set before the CPU (or modules) can access the on-chip SRAM (see Chapter 5, “Static RAM (SRAM)” for more information. MOTOROLA Chapter 8. System Control Module (SCM) 0000_0000_0000_0000 0000_0000_0000_0000...
The core watchdog timer can be enabled or disabled through CWCR[CWE]. By default it is disabled. If enabled, the watchdog timer requires the NOTE — CWDR See Note IPSBAR + 0x010 Description MCF5282 User’s Manual — MOTOROLA...
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The CWCR controls the software watchdog timer, time-out periods, and software watchdog timer transfer acknowledge. The register can be read at any time, but can be written only if the CWT is not pending. At system reset, the software watchdog timer is disabled. MOTOROLA Chapter 8. System Control Module (SCM) NOTE...
0000_0000 IPSBAR + 0x011 Description CWT [2:0] CWT Time-Out Period Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency MCF5282 User’s Manual CWTAVAL CWTIC MOTOROLA...
MBus masters (M0–M3 in Figure 8-6) has access to the external buses. The function of the arbitration logic is described in this section. MOTOROLA Chapter 8. System Control Module (SCM) Internal Bus Arbitration...
The initial state of the master priorities is M3 > M2 > M1 > M0. System software should guarantee that the programmed Mn_PRTY fields are unique, otherwise the hardware defaults to the initial-state priorities. MOTOROLA Chapter 8. System Control Module (SCM) Internal Bus Arbitration...
The encodings for this field are shown in Table 8-11. Table 8-11. PACR ACCESSCTRL Bit Encodings Bits Table 8-12. Peripheral Access Control Registers (PACRs) IPSBAR Offset 0x024 0x025 0x026 MOTOROLA Chapter 8. System Control Module (SCM) ACCESS_CTRL1 LOCK0 0000_0000 IPSBAR + 0x24 + Offset Description Supervisor Mode...
0x07FF_FFFF 8-20 Modules Protected Ports, CCM, PMM, Reset controller, Clock, EPORT, WDOG, PIT0–PIT3, QADC, GPTA, GPTB, FlexCAN, CFM (Control) CFM (Flash module’s backdoor access for programming or access by a bus master other than the core) MCF5282 User’s Manual MOTOROLA...
2x to 9x the reference frequency and has a post divider capable of reducing this synthesized frequency without disturbing the PLL. The PLL reference can be either a crystal oscillator or an external clock. MOTOROLA Chapter 9. Clock Module...
Exit not caused by clock module, but clock sources are re-enabled and normal clocking Normal MCF5282 User’s Manual Mode Exit clocking resumes upon mode exit clocking resumes upon mode exit resumes upon mode exit Exit not caused by clock module MOTOROLA...
Figure shows a block diagram of the entire clock module. The PLL block in this diagram is expanded in detail in Figure 9-2. EXTAL XTAL EXTERNAL CLOCK STPMD[1:0] STOP MODE Figure 9-1. Clock Module Block Diagram MOTOROLA CLKMOD[1:0] RSTOUT REFERENCE CLOCK PLLREF LOCEN LOLRE...
0 No reset on loss of lock Note: In external clock mode, the LOLRE bit has no effect. MFD1 MFD0 LOCRE 0010_0001 FWKUP — STPMD1 0000_0000 IPSBAR + 0x0012_0000 Description MCF5282 User’s Manual RFD2 RFD1 RFD0 STPMD0 — — MOTOROLA...
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Note: In external clock mode, the LOCEN bit has no effect DISCLK Disable CLKOUT determines whether CLKOUT is driven. Setting the DISCLK bit holds CLKOUT low. 1 CLKOUT disabled 0 CLKOUT enabled MOTOROLA Description in normal PLL mode. (4x) (6x) (8x) 000 (÷...
PLL. The power-on reset circuit uses the LOCK bit as a condition for releasing reset. If operating in external clock mode, LOCK remains cleared after reset. 1 PLL locked 0 PLL not locked MOTOROLA Description Chapter 9. Clock Module Memory Map and Registers...
Table 9-7 shows the clockout frequency to clockin frequency relationships for the possible system clock modes. 9-10 Description Clock Mode External clock mode 1:1 PLL mode Normal PLL mode with external clock reference Normal PLL mode with crystal reference MCF5282 User’s Manual MOTOROLA...
MFD factor that can be paired with an RFD factor to provide the required frequency. 2. Write a value of RFD (from step 1) + 1 to the RFD field of the SYNCR. MOTOROLA PLL Options × 2(MFD + 2)/2 CAUTION Chapter 9.
MFD divides by. For example, if the MFD divides the VCO frequency by six, the PLL is frequency locked when the VCO MOTOROLA 0 ≤ MFD < 2 2 ≤ MFD < 6 6 ≤...
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Figure 9-6 shows the sequence for detecting locked and non-locked conditions. In external clock mode, the PLL is disabled and cannot lock. 9-14 MCF5282 User’s Manual MOTOROLA...
(RSR) to determine if a loss of lock caused the reset. See Section 28.4.2, “Reset Status Register (RSR).” To exit reset in PLL mode, the reference must be present, and the PLL must achieve lock. MOTOROLA Loss of Lock Detected Set Tight Lock Criteria...
The LOC circuit monitors the reference and feedback inputs to the PFD. See Figure 9-5. 9-16 NOTE Reference Failure Alternate Clock Selected by LOC Circuit Until Reset PLL self-clocked mode None MCF5282 User’s Manual PLL Failure Alternate Clock Selected by LOC Circuit Until Reset PLL reference MOTOROLA...
X X X X — 0 0 0 Off Off 0 Lose lock, f.b. clock, reference clock X 0 0 Off Off 1 Lose lock, f.b. clock, reference clock MOTOROLA PLL Action MODE During Stop — Lose reference Stuck clock Regain ‘LK...
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LOCS not set because LOCEN = 0 ‘LC — — — ‘LC ‘LC LOCS not set because LOCEN = 0 ‘LC 0–>1 ‘LC ‘LC — — — 0–>1 ‘LC ‘LC — — — Reset immediately ‘LC — — — Reset immediately MOTOROLA...
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1 0 0 Off On 1 Lose lock, f.b. clock 1 0 0 On On 0 — 1 0 0 On On 1 — 1 0 1 On On X — MOTOROLA PLL Action MODE During Stop Regain ‘LK No regain Stuck Regain ‘LK...
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‘LC=expecting previous value of LOCS before entering stop 1–>‘LC= current value is 1 until clock is regained which then will be the previous value before entering stop 1–> =current value is 1 until clock is regained but CLK is never expected to regain MOTOROLA PLL Action MODE During Stop —...
Level 7 interrupts are treated as non-maskable and edge-sensitive within the processor, while levels 1-6 are treated as level-sensitive and may be masked depending on the value of the SR[I] field. For MOTOROLA Chapter 10. Interrupt Controller Modules 10-1...
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During the execution of the service routine, the appropriate actions must be performed on the peripheral to negate the interrupt request. For more information on exception processing, see the ColdFire Programmer’s Reference Manual at http://www.motorola.com/coldfire 10-2 MCF5282 User’s Manual MOTOROLA...
10.1.1.2 Interrupt Prioritization As an active request is detected, it is translated into the programmed interrupt level, and the resulting 7-bit decoded priority level (IRQ[7:1]) is driven out of the interrupt controller. MOTOROLA Chapter 10. Interrupt Controller Modules 68K/ColdFire Interrupt Architecture Overview...
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This design provides unique vector capability for all interrupt requests, regardless of the “complexity” of the peripheral device. Vector numbers 64-71, and 91-255 are unused. 10-4 then vector_number = then vector_number = then vector_number = then vector_number = en the bit position within the source to the actual MCF5282 User’s Manual MOTOROLA...
IMRLn bit is set. 0 The corresponding interrupt source does not have an interrupt pending 1 The corresponding interrupt source has an interrupt pending — Reserved, should be cleared. MOTOROLA Chapter 10. Interrupt Controller Modules INT[63:48] 0000_0000_0000_0000 INT[47:32]...
INTFRC Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes. 0 No interrupt forced on corresponding interrupt source 1 Force an interrupt on the corresponding source MOTOROLA Chapter 10. Interrupt Controller Modules Description INTFRCH[63:48]...
0 There are no active interrupts at this level 1 There is an active interrupt at this level — Reserved 10-10 INTFRCL[31:16] 0000_0000_0000_0000 INTFRCL[16:1] 0000_0000_0000_0000 IPSBAR + 0xC14, 0xD14 Description IRQ[7:1] 0000_0000 IPSBAR + 0xC18, 0xD18 Description MCF5282 User’s Manual — — MOTOROLA...
Failure to program the ICRnx registers in this manner can result in undefined behavior. If a specific interrupt request is completely unused, the ICRnx value can remain in its reset (and disabled) state. MOTOROLA Chapter 10. Interrupt Controller Modules LEVEL...
Write EPF3 = 1 Write EPF4 = 1 Write EPF5 = 1 Write EPF6 = 1 Write EPF7 = 1 Cleared when service complete Cleared when service complete Cleared when service complete Cleared when service complete MCF5282 User’s Manual Flag Clearing Mechanism MOTOROLA...
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PAOVF Pulse accumulator overflow Timer channel 0 Timer channel 1 Timer channel 2 Timer channel 3 MOTOROLA Chapter 10. Interrupt Controller Modules Source Description Not used Write IIF = 0 See QIR description Write CAP = 1 or REF = 1...
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Write PIF = 1 of write PMR Write PIF = 1 of write PMR Write PIF = 1 of write PMR Write CBEIF = 1 Cleared automatically Cleared automatically Cleared automatically Not Used MCF5282 User’s Manual Flag Clearing Mechanism MOTOROLA...
The vector number is supplied as the data for the byte-sized IACK read cycle. In addition to providing the vector number, the interrupt controller also loads the level and priority number for the level into the IACKLPR register, where it may be retrieved later. MOTOROLA Chapter 10. Interrupt Controller Modules Source Description...
INTC0 interrupt will be serviced first. If INTC1 has an active interrupt that has a higher level or priority than the highest INTC0 interrupt, then the INTC1 interrupt will be serviced first. 10-16 VECTOR 0000_0000 See Table 10-2 and Table 10-3 for register offsets Description MCF5282 User’s Manual MOTOROLA...
SCM where it is combined with the wakeup signals from the other interrupt controller and then to the PLL module to re-enable the device’s clock trees and resume processing. MOTOROLA Chapter 10. Interrupt Controller Modules Low-Power Wakeup Operation NOTE...
This section describes the operation of the EPORT module in low-power modes. For more information on low-power modes, see Chapter 7, “Power Management.” Table 11-1 shows EPORT module operation in low-power modes, and describes how this module may exit from each mode. MOTOROLA Stop Mode Edge Detect...
Any IRQx Interrupt at or above level in LPICR Normal Any IRQx Interrupt at or above level in LPICR Level-sensing Only Any IRQx Interrupt set for level-sensing at or above level in LPICR NOTE MCF5282 User’s Manual Mode Exit MOTOROLA...
• The EPORT data register (EPDR) holds the data to be driven to the pins. • The EPORT pin data register (EPPDR) reflects the current state of the pins. • The EPORT flag register (EPFR) individually latches EPORT edge events. MOTOROLA EPORT Pin Assignment Register (EPPAR) EPORT Interrupt Enable Register (EPIER) EPORT Pin Data Register (EPPDR) Chapter 11.
(EPPARx = 00), pin transitions do not affect this register. 1 Selected edge for IRQx pin has been detected. 0 Selected edge for IRQx pin has not been detected. — Reserved, should be cleared. MOTOROLA Chapter 11. Edge Port Module (EPORT) 11-7...
These generated signals provide byte data select signals, which are decoded from the transfer size, A1, and A0 signals in addition to the programmed port size and burstability of the memory accessed, as Table 12-2 shows. MOTOROLA NOTE Description Chapter 12. Chip Select Module...
Table 12-2 shows the interaction of the byte-enable/byte-write enables with related signals. Table 12-2. Byte Enables/Byte Write Enable Signal Settings Transfer Size Port Size Byte 8-bit 16-bit 32-bit Word 8-bit 16-bit 32-bit Longword 8-bit 16-bit 32-bit Line 8-bit 16-bit 32-bit 12-2 D[31:24] D[23:16] MCF5282 User’s Manual D[15:8] D[7:0] MOTOROLA...
• If the address and attribute match both DACRs or a DACR and a CSAR, the operation is undefined. Table 12-3 shows the type of access as a function of match in the CSARs and DACRs. MOTOROLA Chapter 12. Chip Select Module Chip Select Operation...
1 Only read accesses are allowed. — Reserved, should be cleared. Alternate master. When AM = 0 during a DMA access, SC, SD, UC, and UD are don’t cares in the chip select decode. MOTOROLA Description 16 15 — Unitialized 0x0B4 (CSMR4);...
1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports and line writes to 8-, 16-, and 32-bit ports. 2–0 — Reserved, should be cleared. MOTOROLA Description Chapter 12. Chip Select Module Chip Select Registers 12-9...
Data transfers between the MCF5282 and other devices involve the following signals: • Address bus (A[23:0]) • Data bus (D[31:0]) • Control signals (TS and TA) • CSn, OE, BS • Attribute signals (R/W, SIZ, and TIP) 13-2 Description MCF5282 User’s Manual CLKOUT Edge Rising Rising Rising MOTOROLA...
13.4.1 Bus Cycle Execution When a bus cycle is initiated, the MCF5282 first compares the address of that bus cycle with the base address and mask configurations programmed for chip selects 0–7 MOTOROLA Chapter 13. External Interface Module (EIM) D[31:24]...
CSCRs. If TA is not generated internally, the system must provide it externally. 13-4 Number of DACR Matches External Defined by CSCR External, burst-inhibited, 32-bit Defined by DACRs Undefined Undefined Multiple Undefined Multiple Undefined Multiple Undefined MCF5282 User’s Manual Type of Access MOTOROLA...
TS is negated on the rising edge of CLKOUT in S2. (skipped fast termination) Write The data bus is driven out of high impedance as data is placed on the bus on the rising edge of CLKOUT. MOTOROLA Chapter 13. External Interface Module (EIM) Fast Termination Wait States Table 13-3.
13.4.3 Read Cycle During a read cycle, the MCF5282 receives data from memory or from a peripheral device. Figure 13-5 is a read cycle flowchart. 13-6 Description NOTE: MCF5282 User’s Manual MOTOROLA...
Note the following characteristics of a basic read: • In S3, data is made available by the external device on the falling edge of CLKOUT and is sampled on the rising edge of CLKOUT with TA asserted. MOTOROLA Chapter 13. External Interface Module (EIM) NOTE:...
CLKOUT A[31:0], SIZ[1:0] CSn, BSn D[31:0] Figure 13-8. Basic Write Bus Cycle Table 13-3 describes the six states of a basic write cycle. 13-8 Decode address Store data on D[31:0] Assert TA Negate TA Write MCF5282 User’s Manual System MOTOROLA...
Figure 13-9. Read Cycle with Fast Termination Figure 13-10 shows a write cycle with fast termination. CLKOUT A[31:0], SIZ[1:0] CSn, BSn D[31:0] Figure 13-10. Write Cycle with Fast Termination MOTOROLA Chapter 13. External Interface Module (EIM) Read Write Data Transfer Operation 13-9...
8-bit port, SIZ[1:0] = 00 for the first byte transfer and does not change. The CSCRs can be used to enable bursting for reads, writes, or both. MCF5282 memory space can be declared burst-inhibited for reads and writes by clearing the appropriate 13-10 MCF5282 User’s Manual MOTOROLA...
A byte operand is properly aligned at any address, a word operand is 13-14 S4 S5 Write Write A[3:2] = 01 A[3:2] = 10 Longword Write Fast MCF5282 User’s Manual Write Write A[3:2] = 11 Write Write Fast Fast MOTOROLA...
— Transfer 1 Transfer 2 Byte 1 Figure 13-20. Example of a Misaligned Word Transfer (32-Bit Port) MOTOROLA Chapter 13. External Interface Module (EIM) 24 23 16 15 — Byte 0 —...
Active-low signals, such as SRAS and TA, are indicated with an overbar. 14.1 Overview Figure 14-1 shows the block diagram of the MCF5282 with the signal interface. MOTOROLA NOTE Chapter 14. Signal Descriptions 14-1...
Chip selects CS[6:0] SDRAM row SRAS address strobe SDRAM column SCAS address strobe MOTOROLA NOTE: Function External Memory Interface Define the address of external byte, word, longword, and 16-byte burst accesses. Data bus. Provide the general purpose data path between the MCU and all other devices.
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Serial output Ethernet data. Asserted to indicate a collision. Provides a timing reference for ERXDV, ERXD[3:0], and ERXER. MCF5282 User’s Manual Page 14-21 14-21 14-21 14-22 14-22 14-22 14-22 14-22 14-22 14-22 14-23 14-23 14-23 14-23 14-23 14-23 14-24 14-24 MOTOROLA...
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Transmit serial UTXD[2:0] data output Receive serial URXD[2:0] data input MOTOROLA Function Asserted to indicate that the PHY has valid nibbles present on the MII. Ethernet input data transferred from the PHY to the media access controller (when ERXDV is asserted).
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Provides single-bit communication for debug module commands (DSI). Provides serial data port for loading JTAG boundary scan, bypass, and instruction registers (TDI). MCF5282 User’s Manual Page 14-27 14-27 14-27 14-27 14-27 14-28 14-28 14-29 14-29 14-30 14-30 14-30 14-31 14-31 MOTOROLA...
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Standby power VSTBY Positive supply Ground Table 14-2 lists signals in alphabetical order by abbreviated name. MOTOROLA Function Provides single-bit communication for debug module responses (DSO). Provides serial data port for outputting JTAG logic data (TDO). JTAG test logic clock.
ECOL Asserted to indicate a collision. ECRS Asserted to indicate that the transmit or receive medium is not idle. EMDC Provides a timing reference to the PHY for data transfers on the EMDIO signal. 14-8 Function MCF5282 User’s Manual MOTOROLA...
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Supplies positive power to the core logic and I/O pads. PST[3:0] Indicate core status. VRH, VRL High (VRH) and low (VRL) reference potentials for the analog converter. VDDA, VSSA Isolate the QADC analog circuitry from digital power supply noise. MOTOROLA Function Chapter 14. Signal Descriptions Overview 14-9...
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Asserted during the first CLKOUT cycle of a transfer when address and attributes are valid. UCTS[1:0] Signals UART that it can begin data transmission. URTS[1:0] Automatic UART request to send outputs. URXD[2:0] Receiver serial data inputs. 14-10 Function C interface. C interface. MCF5282 User’s Manual MOTOROLA...
Table 14-4 will operate as described above. All other signals will default to GPIO inputs. Table 14-5. Default Signal Functions After System Signal A[23:0] D[31:0] BS[3:0] SIZ[1:0] MOTOROLA Reset Clock and Reset Signals — — XTAL CLKOUT Debug Support Signals —...
These pins are configured as GPIO ports A, B, C and D in single-chip mode. 14.2.1.3 Byte Strobes (BS[3:0]) The byte strobes (BS[3:0]) define the byte lane of data on the data bus. During accesses, 14-18 Reset High High High MCF5282 User’s Manual MOTOROLA...
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When the device is in normal mode, static bus sizing lets the programmer change data bus width between 8, 16, and 32 bits for each chip select. The SIZ[1:0] outputs specify the data access size of the current external bus reference as shown in Table 14-6. MOTOROLA Chapter 14. Signal Descriptions 14-19...
This pin can also be configured as GPIO PE0 or SYNCB. 14.2.1.11 Chip Selects (CS[6:0]) Each chip select can be programmed for a base address location and for masking addresses, 14-20 Transfer Size Longword Byte Word 16-byte line NOTE: MCF5282 User’s Manual MOTOROLA...
SDRAM memory blocks). These pins is configured as GPIO PSD[2:1] in single-chip mode. 14.2.2.5 SDRAM Clock Enable (SCKE) This output is the SDRAM clock enable. This pin is configured as GPIO PSD0 in single-chip mode. MOTOROLA Chapter 14. Signal Descriptions 14-21...
(see Section 30.6, “Functional Description”). The internal configuration signals are driven to reflect the levels on the external configuration pins to allow for module configuration. 14.2.4.2 CLKMOD[1:0] The state of the CLKMOD[1:0] pins during reset determines the clock mode after reset. 14-22 MCF5282 User’s Manual MOTOROLA...
ETXD0 is the serial output Ethernet data and is only valid during the assertion of ETXEN. This signal is used for 10 Mbps Ethernet data. This signal is also used for MII mode data in conjunction with ETXD[3:1]. MOTOROLA Chapter 14. Signal Descriptions 14-23...
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When the ETXER output is asserted for one or more E_TXCLKs while ETXEN is also asserted, the PHY sends one or more illegal symbols. ETXER has no effect at 10 Mbps or when ETXEN is negated, and applies to MII mode operation. 14-24 MCF5282 User’s Manual MOTOROLA...
14.2.7.4 QSPI Chip Selects (QSPI_CS[3:0]) The synchronous peripheral chip selects (QSPI_CS[3:0]) outputs provide QSPI peripheral chip selects that can be programmed to be active high or low. This pin can also be configured as GPIO PQS[6:3]. MOTOROLA Chapter 14. Signal Descriptions 14-25...
The UTXD[1:0] pins can be configured as GPIO ports PUA2 and PUA0. The UTXD2 output is offered on 3 pins and is a secondary function of the EMDC/ GPIO port PAS4 pin, CANTX/GPIO port PAS2 pin, and SCL/GPIO port PAS0 pin. 14-26 MCF5282 User’s Manual MOTOROLA...
These pins can also be configured as GPIO PTB[3:0]. 14.2.11.3 External Clock Input (SYNCA/SYNCB) These pins are used to clear the clock for each of the two timers, and are provided as a means of synchronization to externally clocked or timed events. MOTOROLA Chapter 14. Signal Descriptions 14-27...
14.2.12.6 DMA Timer 2 Output (DTOUT2) The programmable DMA timer output (DTOUT2) pulse or toggle on various timer events. This pin can also be configured as GPIO PTC0, secondary function UCTS1, or secondary function UCTS0. 14-28 MCF5282 User’s Manual MOTOROLA...
ANZ. This pin can also be configured as GPIO PQB3. 14.2.13.5 QADC Analog Input (AN52/MA0) This PQA signal is the direct analog input AN52. When using external multiplexing this MOTOROLA Chapter 14. Signal Descriptions 14-29...
JTAG instruction register to choose the bypass instruction. When this occurs, JTAG logic is benign and does not interfere with normal MCF5282 functionality. Although TRST is asynchronous, Motorola recommends that it makes an 14-30 MCF5282 User’s Manual...
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Various JTAG operations occur on the rising or falling edge of TCK. Holding TCK high or low for an indefinite period does not cause JTAG test logic to lose state information. If TCK is not used, it must be tied to ground. MOTOROLA Chapter 14. Signal Descriptions 14-31...
Begin execution of RTE instruction Begin one-byte transfer on DDATA Begin two-byte transfer on DDATA Begin three-byte transfer on DDATA Begin four-byte transfer on DDATA Exception Processing Emulator-Mode Exception Processing Processor is stopped Processor is halted MCF5282 User’s Manual MOTOROLA...
This pin is used to provide standby voltage to the RAM array if VDD is lost. 14.2.16.8 Positive Supply (VDD) This pin supplies positive power to the core logic and I/O pads. 14.2.16.9 Ground (VSS) This pin is the negative supply (ground) to the chip. MOTOROLA Chapter 14. Signal Descriptions 14-33...
• SDRAM bank: An internal partition in an SDRAM device. For example, a 64-Mbit SDRAM component might be configured as four 512K x 32 banks. Banks are selected through the SDRAM component’s bank select lines. MOTOROLA Chapter 15. Synchronous DRAM Controller Module 15-1...
Commands are issued to memory using specific encodings on address and control pins. Soon after system reset, a command must be sent to the SDRAM mode register to configure SDRAM operating parameters. MOTOROLA Chapter 15. Synchronous DRAM Controller Module Table 15-1. SDRAM Commands Definition executes;...
DRAM address and control register 0 (DACR0) [p. 15-6] DRAM mask register block 0 (DMR0) [p. 15-8] DRAM address and control register 1 (DACR1) [p. 15-6] DRAM mask register block 1 (DMR1) [p. 15-8] MCF5282 User’s Manual [7:0] — MOTOROLA...
15.625 µs for each row (1031 bus clocks at 66 MHz). This operation is the same as in asynchronous mode. # of bus clocks = 1031 = (RC field + 1) x 16 RC = (1031 bus clocks/16) -1 = 63.44, which rounds to 63; therefore, RC = 0x3F. MOTOROLA Chapter 15. Synchronous DRAM Controller Module RTIM...
— Reserved, should be cleared. 15-6 — — CASL — Uninitialized IPSBAR+0x048 (DACR0); 0x050 (DACR1) Description Parameter CASL= 00 command ACTV MCF5282 User’s Manual — IMRS Uninitialized Number of Bus Clocks CASL = 01 CASL= 10 CASL= 11 MOTOROLA —...
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DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the 2–0 — Reserved, should be cleared. MOTOROLA Chapter 15. Synchronous DRAM Controller Module Description Command Bit ) command. Setting IMRS generates a command finishes.
WP — C/I AM SC SD UC UD V Uninitialized IPSBAR + 0x04C (DMR0), 0x054 (DMR1) Description MOVEC instruction or interrupt acknowledge cycle DMA master Any supervisor-only instruction access Any data fetched during the instruction access Any user instruction Any user data MCF5282 User’s Manual Access Definition MOTOROLA...
In burst page mode, there are multiple read or write operations for every command in the SDRAM if the requested transfer size exceeds ACTV MOTOROLA Chapter 15. Synchronous DRAM Controller Module D[31:24] D[23:16] D[15:8]...
) of 2 system clock cycles. Note that data is available The next bus cycle is initiated sooner, but cannot begin an delay completes. ACTV MCF5282 User’s Manual READ WRITE command is generated to prepare is equal to the read command is executed one cycle Column READ PALL MOTOROLA...
At this time, an internal refresh request flag is set and the counter begins counting down again. The DRAM controller completes any active burst operation and then performs operation. The DRAM controller then initiates a refresh cycle and clears the refresh PALL MOTOROLA Chapter 15. Synchronous DRAM Controller Module Column Column Column...
SELF command is sent to the DRAM controller. Figure 15-9 shows the self-refresh operation. 15-16 is finished. Because both chip selects are active during the MCF5282 User’s Manual command is ACTV delay ACTV command is then ACTV SELFX MOTOROLA ACTV...
DMR[BAM] if the mode register configuration does not fall in the address range determined by the address mask bits. After the mode register is set, DMR mask bits can be restored to their desired configuration. MOTOROLA Chapter 15. Synchronous DRAM Controller Module SELF...
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The important thing is that the address output of that access needs the correct mode programming information on the correct address bits. Figure 15-10 shows the command, which occurs in the first clock of the bus cycle. 15-18 MCF5282 User’s Manual MOTOROLA...
512-Kbyte block of each 1-Mbyte partition in the SDRAM (each 16 Mbytes). The starting address of the SDRAM is 0xFF88_0000. Continuous page mode feature is used. 15-20 RTIM 0000_0000_0010_0110 0026 Description value is 70 ns, indicating a 3-clock refresh-to- MCF5282 User’s Manual A10 = CMD timing. ACTV MOTOROLA...
Although A[31:20] corresponds to the address programmed in DACR0, according to how DACR0 and DMR0 are initialized, bit 19 must be set to hit in the SDRAM. Thus, before the mode register bit is set, DMR0[19] must be set to enable masking. MOTOROLA Chapter 15. Synchronous DRAM Controller Module SDRAM Pins...
(SARn), destination address register (DARn), byte count register (BCRn), control register (DCRn), and status register (DSRn). Transfers are dual address to on-chip devices, such as UART, SDRAM controller, and GPIOs. MOTOROLA NOTE Chapter 16. DMA Controller Module...
Channel System Bus Address Enables System Bus Size Current Master Attributes Control Arbitration/ Control Data Path Control Figure 16-1. DMA Signal Diagram NOTE MCF5282 User’s Manual Channel 3 SAR3 DAR3 Interrupts BCR3 DCR3 DSR3 Bus Interface Registered Bus Signals MOTOROLA...
3. Channel termination—Occurs after the operation is finished, either successfully or due to an error. The channel indicates the operation status in the channel’s DSR, described in Section 16.4.5, “DMA Status Registers (DSR0–DSR3).” 16-4 Control and Data Memory/ Peripheral Memory/ Peripheral Control and Data MCF5282 User’s Manual MOTOROLA...
The DMA module originally supported a left-justified 16-bit byte count register (BCR). This function was later reimplemented as a right-justified 24-bit BCR. The operation of the DMA and the interpretation of the BCR is controlled by the MPARK[BCR24BIT]. See Section 8.5.3, “Bus Master Park Register (MPARK)" for more details. MOTOROLA DMA Controller Module Programming Model [23:16] Source address register 0 (SAR0) [p.
Figure 16-7 shows BCRn for BCR24BIT = 0. Field Reset Address Figure 16-7. Byte Count Registers (BCRn)—BCR24BIT = 0 DSRn[DONE], shown in Figure 16-9, is set when the block transfer is complete. MOTOROLA DMA Controller Module Programming Model NOTE NOTE 0000_0000_0000_0000_0000_0000 IPSBAR + 0x10C, 0x14C, 0x18C, 0x1CC...
Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. 16-8 — — SINC 0000_0000_0000_0000 — IPSBAR + 0x108, 0x148, 0x188, 0x1C8 Description MCF5282 User’s Manual SSIZE DINC DSIZE START MOTOROLA...
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0 DMA inactive 1 The DMA begins the transfer in accordance to the values in the control registers. START is cleared automatically after one system clock and is always read as logic 0. MOTOROLA DMA Controller Module Programming Model Description...
0 No request is pending or the channel is currently active. Cleared when the channel is selected. 1 The DMA channel has a transfer remaining and the channel is not selected. 16-10 Description — 0000_0000 IPSBAR + 0x110, 0x150, 0x190, 0x1D0 Description MCF5282 User’s Manual DONE MOTOROLA...
• Cycle-steal mode (DCRn[CS] = 1)—Only one complete transfer from source to destination occurs for each request. If DCRn[EEXT] is set, a request can be either internal or external. An internal request is selected by setting DCRn[START]. An MOTOROLA DMA Controller Module Functional Description Description access, Chapter 16.
If the BCRn is a multiple of DCRn[BWC], the DMA request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters. If a termination error occurs, DSRn[BES,DONE] are set and DMA transactions stop. 16-12 MCF5282 User’s Manual MOTOROLA...
SINC,DINC] and on the starting address. Increment values can be 1, 2, 4, or 16 for byte, word, longword, or 16-byte line transfers, respectively. If the address register is programmed to remain unchanged (no count), the register is not incremented after the data transfer. MOTOROLA DMA Controller Module Functional Description Chapter 16. DMA Controller Module 16-13...
4. Repeat longwords until SARn = 0x00F0. 5. Read byte from 0x00F0—write byte, increment SARn. If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the configured size. 16-14 MCF5282 User’s Manual MOTOROLA...
The processor can read DSRn to determine whether the transfer terminated successfully or with an error. DSRn[DONE] is then written with a one to clear the interrupt and the DONE and error bits. MOTOROLA DMA Controller Module Functional Description Chapter 16. DMA Controller Module...
50MHz • Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of 25 MHz • Retransmission from transmit FIFO following a collision (no processor bus utilization) MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-1...
(EMDC/EMDIO pins) to the transceiver. Refer to the MMFR and MSCR register descriptions as well as the section on the MII for a description of how to read and write registers in the transceiver via this interface. 17-2 MCF5282 User’s Manual MOTOROLA...
Address recognition options are discussed in detail in Section 17.4.8, “Ethernet Address Recognition”. 17.2.4 Internal Loopback Internal loopback mode is selected via RCR[LOOP]. Loopback mode is discussed in detail in Section 17.4.13, “Internal and External Loopback”. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-3...
(Ethernet driver) interface for transmitting and receiving frames. Following the software initialization and operation sections are sections providing a detailed description of the functions of the FEC. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) NOTE Chapter 21, “DMA...
17.4.4 User Initialization (After Asserting ECR[ETHER_EN]) After asserting ECR[ETHER_EN], the user can set up the buffer/frame descriptors and write to the TDAR and RDAR. Refer to Section 17.6, “Buffer Descriptors” for more details. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Description MSCR (optional)
After the transmitter has stopped the GRA (graceful stop complete) interrupt is asserted. If TCR[GTS] is cleared, the FEC resumes transmission with the next frame. The Ethernet controller transmits bytes least significant bit first. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-9...
(RFINT bit in EIR, maskable by RFIEN bit in EIMR), indicating that a frame has been received and is in memory. The Ethernet controller then waits for a new frame. The Ethernet controller receives serial data LSB first. 17-10 MCF5282 User’s Manual MOTOROLA...
MISS bit in the receive buffer descriptor is set; otherwise, the frame will be rejected. In general, when a frame is rejected, it is flushed from the FIFO. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-11...
Set MC bit in Rcv BD if multicast Set BC bit in Rcv BD if broadcast MCF5282 User’s Manual True Receive Frame Set MC bit in RCV BD if multicast True True Pause Frame False Reject Frame Flush from FIFO Receive Frame MOTOROLA...
56/64 (or 87.5%) of the group address frames from reaching memory. Those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Receive Address...
(TCR[RFC_PAUSE]) status bit is asserted while the transmitter is paused due to reception of a pause frame. 17-16 6-bit Hash (in Hash Decimal hex) Value 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x0180_c200_0001 or Physical Address 0x8808 0x0001 0x0000 to 0xFFFF MCF5282 User’s Manual MOTOROLA...
17.4.13 Internal and External Loopback Both internal and external loopback are supported by the Ethernet controller. In loopback mode, both of the FIFOs are used and the FEC actually operates in a full-duplex fashion. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-17...
LC bit is set in the EIR register. The FEC will then continue to the next transmit buffer descriptor and begin transmitting the next frame. The “LC” interrupt will be asserted if enabled in the EIMR register. 17-18 MCF5282 User’s Manual MOTOROLA...
When the receive frame length exceeds MAX_FL bytes the BABR interrupt will be generated, and the LG bit in the end of frame RxBD will be set. The frame is not truncated unless the frame length exceeds 2047 bytes). MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-19...
Name Width Interrupt Event Register EIMR Interrupt Mask Register RDAR Receive Descriptor Active Register TDAR Transmit Descriptor Active Register Ethernet Control Register MDATA MII Data Register MSCR MII Speed Control Register MIBC MIB Control/Status Register MCF5282 User’s Manual Description MOTOROLA...
Package objects are supported by the FEC but do not require counters in the MIB block. In addition, some of the recommended package objects which are supported do not require MIB counters. Counters for transmit and receive full duplex flow control frames are included as well. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Name Width...
These interrupts can be divided into operational interrupts, transceiver/network error interrupts, and internal error interrupts. Interrupts which may occur in normal operation are GRA, TXF, TXB, RXF, RXB, and MII. Interrupts resulting from errors/problems detected MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Programming Model...
Babbling transmit error. This bit indicates that the transmitted frame length has exceeded RCR[MAX_FL] bytes. This condition is usually caused by a frame that is too long being placed into the transmit data buffer(s). Truncation does not occur. MCF5282 User’s Manual — MOTOROLA...
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Bits Name EBERR 18–0 — MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Description Graceful stop complete. This interrupt will be asserted for one of three reasons. Graceful stop means that the transmitter is put into a pause state after completion of the frame currently being transmitted.
The corresponding EIR bit reflects the state of the interrupt signal even if the corresponding EIMR bit is set. 0 The corresponding interrupt source is masked. 1 The corresponding interrupt source is not masked. Reserved, should be cleared. MCF5282 User’s Manual — MOTOROLA...
The TDAR register is cleared at reset, when ECR[ETHER_EN] is cleared, or when ECR[RESET] is set. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) R_DES_ACTIVE 0000_0000_0000_0000 —...
Reserved, should be cleared. Cleared by the FEC device whenever no additional “ready” descriptors remain in the transmit ring. Also cleared when ECR[ETHER_EN] is cleared. Reserved, should be cleared. — 1111_0000_0000_0000 — 0000_0000_0000_0000 IPSBAR + 0x1024 MCF5282 User’s Manual — ETHER_EN RESET MOTOROLA...
Reset Field Reset Address Figure 17-9. MII Management Frame Register (MMFR) MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Description Reserved. When this bit is set, the FEC is enabled, and reception and transmission are possible. When this bit is cleared, reception is immediately stopped and transmission is stopped after a bad CRC is appended to any currently transmitted frame.
PHY device. Turn around. This field must be programmed to 10 to generate a valid MII management frame. Management frame data. This is the field for data to be written to or read from the PHY register. MCF5282 User’s Manual MOTOROLA...
EMDC. The EMDC generated will have a 50% duty cycle except when MII_SPEED is changed during operation (change will take effect following either a rising or falling edge of EMDC). MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) —...
A read/write control bit. If set, the MIB logic will halt and not update any MIB counters. A read-only status bit. If set the MIB block is not currently updating any MIB counters. Reserved. MCF5282 User’s Manual EMDC frequency 2.5 MHz 2.36 MHz 2.5 MHz 2.5 MHz 2.5 MHz MOTOROLA...
Name 31–27 — 26–16 MAX_FL 15–6 — BC_REJ PROM MII_MODE MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) MAX_FL 0000_0101_1110_1110 — FCE BC_REJ PROM MII_MODE DRT LOOP 0000_0000_0000_0001 IPSBAR + 0x1084 Description Reserved, should be cleared. Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the end of the frame.
The system clock is substituted for the ETXCLK when LOOP is asserted. DRT must be set to zero when asserting LOOP. — 0000_0000_0000_0000 RFC_PAUSE TFC_PAUSE 0000_0000_0000_0000 IPSBAR + 0x10C4 MCF5282 User’s Manual FDEN HBC GTS MOTOROLA...
(Destination Address) field of receive frames with an individual DA. In addition, this register is used in bytes 0 through 3 of the 6-byte source address field when transmitting PAUSE frames. This register is not reset and must be initialized by the user. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Description Reserved, should be cleared.
Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits 7:0) of the 6-byte individual address to be used for exact match, and the Source Address field in PAUSE frames. PADDR2 Uninitialized TYPE 1000_1000_0000_1000 IPSBAR + 0x10E8 MCF5282 User’s Manual MOTOROLA...
DA field of receive frames with an individual DA. This register is not reset and must be initialized by the user. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Description...
The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32. IADDR2 Uninitialized IADDR2 Uninitialized IPSBAR + 0x111C MCF5282 User’s Manual MOTOROLA...
The GALR register is written by the user. This register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. This register must be initialized by the user. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Description...
Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0. — 0000_0000_0000_0000 — 0000_0000_0000_0000 IPSBAR + 0x1144 MCF5282 User’s Manual X_WMRK MOTOROLA...
Name 31–10 — 9–2 R_BOUND 1–0 — MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Descriptions Reserved, should be cleared. Number of bytes written to transmit FIFO before transmission of a frame begins 0x 64 bytes written 10 128 bytes written 11 192 bytes written —...
0000_0101_0000_0000 IPSBAR + 0x1150 Descriptions Reserved, read as 0 (except bit 10, which is read as 1). Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs. Reserved, read as 0. MCF5282 User’s Manual — MOTOROLA...
This register is not reset and must be initialized by the user prior to operation. Field Reset Field Reset Address Figure 17-25. Transmit Buffer Descriptor Ring Start Register (ETDSR) MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) R_DES_START Uninitialized R_DES_START Uninitialized IPSBAR + 0x1180 Descriptions Reserved, should be cleared.
Reserved, should be cleared. — Uninitialized R_BUF_SIZE Uninitialized IPSBAR + 0x11B8 Descriptions Reserved, should be written to 0 by the host processor. Receive buffer size. Reserved, should be written to 0 by the host processor. MCF5282 User’s Manual — MOTOROLA...
TCP header in a 2nd buffer, IP header in a 3rd buffer, Ethernet/IEEE 802.3 header in a 4th buffer. The Ethernet MAC does not prepend the Ethernet header (destination address, source address, length/type field(s)), so this must be MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-45...
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The frame status/length information is written into the receive FIFO following the end of the frame (as a single 32-bit word) by the receive logic. The length 17-46 MCF5282 User’s Manual MOTOROLA...
If this bit is set the CR bit will not be set. — Reserved. Receive CRC error. Written by the FEC. This frame contains a CRC error and is an integral number of octets in length. This bit is valid only if the L-bit is set. MCF5282 User’s Manual Description MOTOROLA...
Transmit frame status is indicated via individual interrupt bits (error conditions) and in statistic counters in the MIB block. See Section 17.5.3, “MIB Block Counters Memory Map” for more details. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Field Name Overrun. Written by the FEC. A receive FIFO overrun occurred during frame reception.
1 Transmit the CRC sequence after the last data byte. Append bad CRC. Written by user (only valid if L = 1). 0 No effect 1 Transmit the CRC sequence inverted after the last data byte (regardless of TC value). — Reserved. MCF5282 User’s Manual Description MOTOROLA...
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BD for the frame. The driver should follow that with a write to TDAR which will trigger the FEC to poll the next BD in the ring. MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) Field Name Data Length Data Length, written by user.
In doze mode with the WCR[DOZE] bit cleared, the watchdog timer continues to operate normally. Watchdog timer operation stops in stop mode. When stop mode is exited, the watchdog timer continues to operate in its pre-stop mode state. MOTOROLA Watchdog Operation Upon Watchdog reset stopped otherwise...
However, writing any value other than 0x5555 or 0xAAAA to WSR resets the servicing sequence, requiring both values to be written to keep the watchdog timer from causing a reset. MOTOROLA Description WC13...
Any IRQx Interrupt at or above level in LPICR stopped otherwise Any IRQx Interrupt at or above level in LPICR stopped otherwise Stopped No. Any IRQx Interrupt will be serviced upon normal stopped otherwise exit from halted mode MCF5282 User’s Manual Mode Exit MOTOROLA...
• The PIT control and status register (PCSR) configures the timer’s operation. • The PIT modulus register (PMR) determines the timer modulus reload value. • The PIT count register (PCNTR) provides visibility to the counter value. MOTOROLA Chapter 19. Programmable Interrupt Timer Modules (PIT0–PIT3) Bits 15–8...
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PIT counter. The prescaler counter is reset anytime a new value is loaded into the PIT counter and also during reset. Reading the PMR returns the value written in the modulus latch. Reset initializes PMR to 0xFFFF. MOTOROLA Chapter 19. Programmable Interrupt Timer Modules (PIT0–PIT3) Memory Map and Registers...
0x0000. If the PIE bit is set in PCSR, the PIF flag issues an interrupt request to the CPU. 19-6 PM13 PM12 PM11 1111_1111 1111_1111 PC13 PC12 PC11 1111_1111 1111_1111 MCF5282 User’s Manual PM10 PC10 MOTOROLA...
The 16-bit PIT counter and prescaler supports different timeout periods. The prescaler divides the system clock as selected by the PRE[3:0] bits in PCSR. The PM[15:0] bits in PMR select the timeout period. Timeout period MOTOROLA Chapter 19. Programmable Interrupt Timer Modules (PIT0–PIT3) 0x0001 0x0000...
The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR. 19-8 MCF5282 User’s Manual MOTOROLA...
The GPTn[2:0] pins are for channel 2–0 input capture and output compare functions. These pins are available for general-purpose input/output (I/O) when not configured for timer functions. MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) Watchdog Operation Normal...
2:0 compares. For each OC3M bit that is set, the output compare action reflects the corresponding OC3D bit. 20.5.5 GPT Counter Register (GPTCNT) Field Reset Address Figure 20-6. GPT Counter Register (GPTCNT) MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) Description — 0000_0000 IPSBAR + 0x1A_0003, 0x1B_0003 Description...
Writing logic 1s to the flags clears them only when TFFCA is clear. 1 Fast flag clearing 0 Normal flag clearing 3–0 — Reserved, should be cleared. 20-8 Description — TFFCA 0000_0000 IPSBAR + 0x1A_0006, 0x1B_0006 Description MCF5282 User’s Manual — MOTOROLA...
0 Toggle output compare pin on overflow feature disabled 20.5.8 GPT Control Register 1 (GPTCTL1) Field Reset Address Figure 20-10. GPT Control Register 1 (GPTCTL1) MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) Write GPTFLG1 Register Data Bit n TFFCA —...
111 Prescaler divisor 128 Note: The newly selected prescaled clock does not take effect until the next synchronized edge of the prescaled clock when the clock count transitions to 0x0000.) MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) Description —...
Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any access to the GPT counter registers clears GPT flag register 2. 20-12 — 0000_0000 IPSBAR + 0x1A_000E, 0x1B_000E Description — 0000_0000 IPSBAR + 0x1A_000F, 0x1B_000F Description MCF5282 User’s Manual MOTOROLA...
To ensure coherent reading of the PA counter, such that the counter does not increment between back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. These bits are read anytime, write anytime. MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) Description...
The output compare 3 mask register masks the bits in the output compare 3 data register. The GPT counter reset enable bit, TCRE, enables channel 3 output compares to MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB)
The PA overflow flag, PAOVF, is set when the PA rolls over from 0xFFFF to 0x0000. The PA overflow interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests. The PA can operate in event counter mode even when the GPT enable bit, GPTEN, is clear. 20-18 NOTE NOTE MCF5282 User’s Manual MOTOROLA...
The PORTTn data direction register controls the data direction of an input capture pin. External pin conditions trigger input captures on input capture pins configured as inputs. MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) NOTE...
CPU Digital input Output compare takes place but does not affect the pin because of the OMn/OLn setting Digital output Output compare takes place but does not affect the pin because of the OMn/OLn setting MOTOROLA...
TOF is set when the GPT counter rolls over from 0xFFFF to 0x0000. If the GPTSCR2[TOI] bit is also set, TOF generates an interrupt request. Clear TOF by writing a 1 to this flag. 20-22 NOTE NOTE NOTE MCF5282 User’s Manual MOTOROLA...
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When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any access to the GPT counter registers clears GPT flag register 2. When TOF is set, it does not inhibit future overflow events. MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) 20-23...
DTRRn registers, the DMA timer may be configured to assert an output signal, generate an interrupt, or initiate a DMA transfer on a particular event. Figure 21-1 is a block diagram of one of the four identical timer modules. MOTOROLA NOTE Chapter 21. DMA Timers (DTIM0–DTIM3)
REF and CAP flags via the internal DMA ACK signal. Field Reset Address IPSBAR + 0x403 (DTER0); + 0x443 (DTER1); 0x483 (DTER2); + 0x4C3 (DTER3) Figure 21-4. DTERn Bit Definitions 21-6 DTXMR n Field Descriptions Description — 0000_0000 R/W (ones clear/zeros have no effect) MCF5282 User’s Manual MOTOROLA...
DTINn cannot simultaneously function as a clocking source and as an input capture pin. Indeterminate operation will result if DTINn is set as the clock source when the input capture mode is used. MOTOROLA Chapter 21. DMA Timers (DTIM0–DTIM3) Description...
— DTINn, the maximum value of DTINn is 1/5 of the system clock, as described in the MCF5282MCF523x Electrical Characteristics. 21-8 CAP (32-bit capture counter value) 0000_0000_0000_0000_0000_0000_0000_0000 32-bit timer counter value count 0000_0000_0000_0000_0000_0000_0000_0000 R/W (to reset) MCF5282 User’s Manual MOTOROLA...
The simple example below uses Timer0 to count time-out loops. A time-out occurs when the reference value, 0xAFAF, is reached. timer0_ex clr.l DO clr.l D1 clr.l D2 MOTOROLA Chapter 21. DMA Timers (DTIM0–DTIM3) Using the DMA Timer Modules NOTE 21-9...
256. For example, if a 66-MHz timer clock is divided by 16, DTMRn[PS] = 0x7F, and the timer is referenced at 0xFBC5 (64,453 decimal), the time-out period is as follows: Time-out period = [1/(66 x 10 21-10 ) x (16) x (127 + 1) x (64,453) = 2.00 s MCF5282 User’s Manual MOTOROLA...
The QSPI module communicates with the integrated ColdFire CPU using internal memory mapped registers starting at IPSBAR + 0x340. See Section 22.5, “Programming Model.” A block diagram of the QSPI module is shown in Figure 22-1. MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module 22-1...
QSPI wrap register (QWR): • The new queue pointer, QWR[NEWQP], points to the first command in the queue. • An internal queue pointer points to the command currently being executed. MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module Hi-Z or Actively Driven...
The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data, 16 words of receive data and 22-4 MCF5282 User’s Manual MOTOROLA...
QWR[CPTQP] shows which queue entries have been executed. The user can query this field to determine which locations in receive RAM contain valid data. MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module Register...
Baud rate is selected by writing a value from 2–255 into QMR[BAUD]. The QSPI uses a prescaler to derive the QSPI_CLK rate from the system clock divided by two. A baud rate value of zero turns off the QSPI_CLK. 22-6 MCF5282 User’s Manual MOTOROLA...
QDLYR[DTL] specifies a delay period. QCR[DT] determines whether the standard delay period (DT = 0) or the specified delay period (DT = 1) is used. The following expression is used to calculate the delay: MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module / [2 × (desired QSPI_CLK baud rate)]...
QSPI clears QDLYR[SPE] and stops, unless wraparound mode is enabled. Wraparound mode is enabled by setting QWR[WREN]. The queue can wrap to pointer address 0x0, or to the address specified by QWR[NEWQP], depending on the state of QWR[WRTO]. 22-8 MCF5282 User’s Manual MOTOROLA...
There are a total of 80 bytes of memory used for transmit, receive, and control data. This memory is accessed indirectly using QAR and QDR. Registers and RAM are written and read by the CPU. MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module Table 22-3. QSPI Registers...
Clock polarity. Defines the clock polarity of QSPI_CLK. 0 The inactive state value of QSPI_CLK is logic level 0. 1 The inactive state value of QSPI_CLK is logic level 1. 22-10 NOTE BITS CPOL CPHA 0000_0001_0000_0100 IPSBAR + 0x340 Description MCF5282 User’s Manual BAUD MOTOROLA...
NEWQP Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a transfer. 22-12 Description ENDQP 0000_0000_0000_0000 IPSBAR + 0x348 Table 22-6. QWR Field Descriptions Description MCF5282 User’s Manual CPTQP NEWQP MOTOROLA...
QWR[HALT]. In wraparound mode, this bit is set every time the command pointed to by QWR[ENDQP] is completed. Writing a 1 to this bit clears it and writing 0 has no effect. MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module WCEFE ABRTE —...
The QDR, shown in Figure 22-9, is used to access QSPI RAM indirectly. The CPU reads and writes all data from and to the QSPI RAM through this register. Field Reset Address Figure 22-9. QSPI Data Register (QDR) 22-14 NOTE — 0000_0000_0000_0000 IPSBAR + 0x350 DATA 0000_0000_0000_0000 IPSBAR + 0x354 MCF5282 User’s Manual ADDR MOTOROLA...
11–8 map directly to QSPI_CS[3:0], respectively. If it is desired to use those bits as a chip select value, then an external demultiplexor must be connected to the QSPI_CS[3:0] pins. 7–0 — Reserved, should be cleared. MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module NOTE DSCK QSPI_CS...
QSPI_CLK frequency of 4.125 MHz (assuming a 66-MHz system clock). 2. Write QDLYR with the desired delays. 22-16 NOTE 0 ns 10 ns 10 ns Figure 22-11. QSPI Timing MCF5282 User’s Manual 20 ns MOTOROLA...
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11. Write QAR with 0x0010 to select the first receive RAM entry. 12. Read QDR to get the received data for each transfer. 13. Repeat steps 5 through 13 to do another transfer. MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module Programming Model...
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Programming Model 22-18 MCF5282 User’s Manual MOTOROLA...
Module (SCM) Interrupt Controller Figure 23-1. Simplified Block Diagram UART0 can be clocked by the DTIN0 pin. UART1 can be clocked by the DTIN1 pin, and UART2 can be clocked by DTIN2. MOTOROLA NOTE UART Internal Channel Serial Control Logic Communications...
• All three UARTs have DMA request capability • Parity, framing, and overrun error detection • False-start bit detection • Line-break detection and generation • Detection of breaks originating in the middle of a character • Start/end break interrupt/status 23-2 MCF5282 User’s Manual MOTOROLA...
Bits per character. Select the number of data bits per character to be sent. The values shown do not include start, parity, or stop bits. 00 5 bits 01 6 bits 10 7 bits 11 8 bits MOTOROLA Description command for the channel was issued. See Section 23.3.5, “UART Parity Mode Parity Type (PT= 0) Even parity...
If CTS is asserted, the character is sent; if it is negated, the channel TXD remains in the high state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. 23-6 TxRTS TxCTS 0000_0000 UMR2n. Description MCF5282 User’s Manual MOTOROLA...
1 No stop bit was detected when the corresponding data character in the FIFO was received. The stop-bit check occurs in the middle of the first stop-bit position. FE is valid only when RxRDY = 1. MOTOROLA Description 5 Bits 6–8 Bits...
To use the system clock for both, set UCSRn to 0xDD. Field Reset Address IPSBAR + 0x204 (UCSR0), 0x244 (UCSR1), 0x284 (UCSR2) Figure 23-5. UART Clock Select Register (UCSRn) Table 23-5 describes UCSRn fields. 23-8 Description RESET ERROR STATUS 0000_0000 Write only MCF5282 User’s Manual command in UCRn. MOTOROLA...
Reset Address Figure 23-6. UART Command Register (UCRn) Table 23-6 describes UCRn fields and commands. Examples in Section 23.5.2, “Transmitter and Receiver Operating Modes,” show how these commands are used. MOTOROLA Description cannot be specified in one command. MISC 0000_0000...
Terminates transmitter operation and clears USRn[TxEMP,TxRDY]. If a character is being sent when the transmitter is disabled, transmission completes before the transmitter becomes inactive. If the transmitter is already disabled, the command has no effect. Reserved, do not use. MCF5282 User’s Manual when reconfiguring the RECEIVER DISABLE MOTOROLA...
USRn[TxRDY] again. Writes to the transmit buffer when the channel’s TxRDY = 0 and when the transmitter is disabled have no effect on the transmit buffer. MOTOROLA Description RC (This field selects a single command) Causes the receiver to stay in its current mode.
CTS is detected asserted at that time, COS is set, which initiates an interrupt if UACRn[IEC] is enabled. 0 The current state of the CTS input is asserted. 1 The current state of the CTS input is negated. 23-12 0000_0000 Write only IPSBAR + 0x20C(UTB0), 0x24C(UTB1), 0x28C(UTB2) Read only Description MCF5282 User’s Manual — MOTOROLA...
UISRn is cleared when the UART module is reset. UIMR Field UISR Field Reset Address IPSBAR + 0x214 (UISR0), 0x254 (UISR1), 0x294 (UISR2) Figure 23-11. UART Interrupt Status/Mask Registers (UISRn/UIMRn) MOTOROLA — 0000_0000 Description NOTE — — 0000_0000 Read only for status, write only for mask Chapter 23.
7–1 — Reserved, should be cleared. Output port output. Controls assertion (UOP1)/negation (UOP0) of RTS output. 0 Not affected. 1 Asserts RTS with a write to UOP1. Negates RTS with a write to UOP0. 23-16 Description MCF5282 User’s Manual MOTOROLA...
The terms ‘assertion’ and ‘negation’ are used to avoid confusion between active-low and active-high signals. ‘Asserted’ indicates that a signal is active, independent of the voltage level; ‘negated’ indicates that a signal is inactive. MOTOROLA UART Module Internal Bus Internal...
• An external clock signal on the DTINn pin that can be divided by 16. When not divided, DTINn provides a synchronous clock mode; when divided by 16, it is asynchronous. 23-18 Description UART RS-232 Transceiver URTSn UCTSn UTXDn URXDn MCF5282 User’s Manual MOTOROLA...
When the system clock is the UART clocking source, it goes through a divide-by-32 prescaler and then passes through the 16-bit divider of the concatenated UBG1n and UBG2n registers. The baud-rate calculation is as follows: Using a 66MHz system clock and letting baud rate = 9600, then MOTOROLA On-Chip Timer Module UART...
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URTSn is negated one bit time after the character in the shift register is completely transmitted. The transmitter must be manually reenabled by reasserting URTSn before the next message is to be sent. Figure 23-20 shows the functional timing information for the transmitter. MOTOROLA Chapter 23. UART Modules 23-21...
The data is then transferred to a receiver holding register and USRn[RxRDY] is set. If the character is less than eight bits, the most significant unused bits in the receiver holding register are cleared. 23-22 Start break MCF5282 User’s Manual Break Stop break transmitted Manually asserted MOTOROLA...
The FIFO stack is used in the UART’s receive buffer logic. The stack consists of three receiver holding registers. The receive buffer consists of the FIFO and a receiver shift register connected to the URXD (see Figure 23-19). Data is assembled in the receiver shift MOTOROLA C5 will be lost Figure 23-21.
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If the receiver is reset, the FIFO stack, URTSn control, all receiver status bits, and interrupts, and DMA requests are reset. No more characters are received until the receiver is reenabled. 23-24 command. Status is updated as RESET ERROR STATUS NOTE MCF5282 User’s Manual MOTOROLA...
Features of this local loop-back mode are as follows: • Transmitter and CPU-to-receiver communications continue normally in this mode. • URXDn input data is ignored MOTOROLA Disabled Figure 23-22. Automatic Echo Disabled Disabled Figure 23-23.
CPU disables the receiver and repeats the process. Functional timing information for multidrop mode is shown in Figure 23-25. 23-26 Disabled Disabled Figure 23-24. Remote Loop-Back MCF5282 User’s Manual URXDn Input UTXDn Input MOTOROLA...
Framing error, overrun error, and break detection operate normally. The A/D bit takes the place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this mode may still contain error detection and correction information. One way to provide error MOTOROLA Master Station ADD1...
(beginning of a break). SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor. 23-28 MCF5282 User’s Manual MOTOROLA...
FIFO stack is popped. However, the DMA may read the full contents of the FIFO stack (if the DMA byte count register is set to 3 and the DMA control register is not set for cycle steal). MOTOROLA Table 23-13. UART Interrupts Interrupt...
Operation ENABLE SERIAL MODULE ERRORS SINIT INITIATE: CHANNEL ENABLE RECEIVER INTERRUPTS CHK1 ASSERT REQUEST TO SEND CALL CHCHK SINITR RETURN SAVE CHANNEL STATUS Figure 23-26. UART Mode Programming Flowchart (Sheet 1 of 5) MOTOROLA Chapter 23. UART Modules 23-31...
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TRANSMITTER READY SNDCHR SEND CHARACTER TO TRANSMITTER RxCHK CHARACTER BEEN RECEIVED Figure 23-26. UART Mode Programming Flowchart (Sheet 2 of 5) 23-32 SET TRANSMITTER- WAITED NEVER-READY FLAG TOO LONG WAITED SET RECEIVER- TOO LONG NEVER-READY FLAG MCF5282 User’s Manual MOTOROLA...
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ERROR FLAG CHRCHK GET CHARACTER FROM RECEIVER SAME AS TRANSMITTED CHARACTER SET INCORRECT CHARACTER FLAG Figure 23-26. UART Mode Programming Flowchart (Sheet 3 of 5) MOTOROLA RSTCHN TO ORIGINAL MODE Chapter 23. UART Modules Operation DISABLE TRANSMITTER RESTORE RETURN 23-33...
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REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS SIRQR Figure 23-26. UART Mode Programming Flowchart (Sheet 4 of 5) 23-34 INCH DOES CHANNEL A RECEIVER HAVE A CHARACTER PLACE CHARACTER IN D0 RETURN MCF5282 User’s Manual MOTOROLA...
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Operation OUTCH TRANSMITTER READY SEND CHARACTER TO TRANSMITTER RETURN Figure 23-26. UART Mode Programming Flowchart (Sheet 5 of 5) MOTOROLA Chapter 23. UART Modules 23-35...
• Arbitration-lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • START and STOP signal generation/detection • Repeated START signal generation MOTOROLA C module, including I C bus standard version 2.1 Chapter 24. I...
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Address Decode C Status Register I/O Register (I2SR) In/Out Data Shift Register Start, Stop, Arbitration Control Address Compare C Module Block Diagram C registers, listed below: MCF5282 User’s Manual Data Data MUX C Data C Address Register (I2DR) (IADR) MOTOROLA...
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START signal (B). After the seven-bit calling address, it sends the R/W bit (C), which tells the slave data transfer direction. Each slave must have a unique address. An I slave address; it cannot be master and slave at the same time. MOTOROLA NOTE C Bus Specification, Interrupt bit set...
After the master has driven SCL low, the slave can drive SCL low for the required period and then release it. If the slave SCL low period is longer than the master SCL low period, the resulting SCL bus signal low period is stretched. MOTOROLA Start counting high period Wait Internal Counter Reset Chapter 24.
C responds to when addressed as a slave. Note that it is 0000_0000 IPSBAR + 0x300 C Address Register (I2ADR) Description C module. Slave mode is the default I MCF5282 User’s Manual [15:8] [7:0] Reserved Reserved Reserved Reserved Reserved — MOTOROLA...
Description C module. If the module is enabled in the middle of a byte C module to lose arbitration, after which bus C interrupt occurs if I2SR[IIF] is also set. MCF5282 User’s Manual — C bus is a receiver. MOTOROLA...
SRW is valid only when a complete transfer has occurred, no other transfers have been initiated, and the I C module is a slave and has an address match. 0 Slave receive, master writing to slave. 1 Slave transmit, master reading from slave. MOTOROLA — 1000_0001 IPSBAR + 0x30C CR Status Register (I2SR) Description Chapter 24.
3. Set I2CR[IEN] to enable the I 4. Modify the I2CR to select or deselect master/slave mode, transmit/receive mode, and interrupt-enable or not. 24-10 Description Data 0000_0000 IPSBAR + 0x310 C Data I/O Register (I2DR) C bus interface system. MCF5282 User’s Manual MOTOROLA...
Sending or receiving a byte sets the I2SR[ICF], which indicates one byte communication is finished. I2SR[IIF] is also set. An interrupt is generated if the interrupt function is enabled during initialization by setting I2CR[IIEN]. Software must first clear I2SR[IIF] in MOTOROLA NOTE C bus module is enabled, C is busy after writing the calling ;Check I2SR[MBB]...
;Transmit next byte of data ;If no ACK, branch to end ;Get value from the transmitting counter ;If no more data, branch to end ;Transmit next byte of data ;Decrease the TXCNT ;Generate a STOP condition ;Return from interrupt MCF5282 User’s Manual MOTOROLA...
Setting RXAK means an end-of-data signal from the master receiver, after which software must switch it from transmitter to receiver mode. Reading I2DR then releases SCL so that the master can generate a STOP signal. MOTOROLA ;Decrease RXCNT ;Last byte to be read ;Check second-to-last byte to be read...
MSTA without signalling a STOP, generates an interrupt to the CPU, and sets IAL to indicate a failed attempt to engage the bus. When considering these cases, the slave service routine should first test IAL and software should clear it if it is set. 24-14 MCF5282 User’s Manual MOTOROLA...
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(Master RX) Write Next Set TXAK =1 Byte to I2DR Switch to Rx Mode Generate Dummy Read from I2DR STOP Signal Figure 24-10. Flow-Chart of Typical I MOTOROLA Clear Master Mode? Last Byte to be Read Address Cycle 2nd Last (Read)
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C Programming Examples 24-16 MCF5282 User’s Manual MOTOROLA...
CAN protocol revision 2.0 is assumed in this document. For details, refer to the CAN protocol revision 2.0 specification. 25.1 Features • Based on and includes all existing Motorola TouCAN module features • Motorola IP interface architecture • Full implementation of the CAN protocol specification version 2.0 —...
Figure 25-1. Each submodule is described in detail in subsequent sections. MB15 MB14 MB13 MB12 0.25k/0.5KB Figure 25-1. FlexCAN Block Diagram and Pinout 25-2 Control Transmitter MB # (0-15) Receiver Bus Interface Unit Internal Bus MCF5282 User’s Manual CANTX CANRX MOTOROLA...
0x1C_007F 0x1C_0080– 0x1C_017F 25.1.2 External Signals The FlexCAN module/CAN transceiver is composed of two signals: CANTX, which is the serial transmitted data, and CANRX, which is the serial received data. MOTOROLA Table 25-1. FlexCAN Memory Map [23:16] Reserved (CANCTRL2) Reserved...
FlexCAN caused by a defective CAN bus or defective stations. 25.3 Message Buffers 25.3.1 Message Buffer Structure Figure 25-3 shows the extended (29 bit) ID message buffer structure. Figure 25-4 displays the standard (11 bit) ID message buffer structure. 25-4 MCF5282 User’s Manual MOTOROLA...
Figure 25-4. Standard ID Message Buffer Structure 25.3.1.1 Common Fields for Extended and Standard Format Frames Table 25-2 describes the message buffer fields that are common to both extended and standard identifier format frames. MOTOROLA 7–4 CODE SRR IDE ID[14-0]...
If a CPU read occurs before 0110 the new frame, new receive code is 0010. 0010 An empty buffer was filled. 0110 A full buffer was filled. 0110 An overrun buffer was filled. Code After Successful Transmission — 1000 0100 1010 1010 MOTOROLA...
25.3.2 Message Buffer Memory Map The message buffer memory map starts at an offset of 0x80 from the FlexCAN’s base address (0x1C_0000). The 256-byte message buffer space is fully used by the 16 message buffer structures. MOTOROLA Description Description Chapter 25. FlexCAN...
(Move In) to the first (that is, lowest entry) matching MB. The value of the free-running timer (which was captured at the beginning of the Identifier field on the CAN bus) is written into the “Time Stamp” field in MOTOROLA NOTE NOTE Chapter 25.
Two receive MBs or more that hold a matching ID to a received frame do not assure reception in the FlexCAN if the user has deactivated the matching MB after FlexCAN has scanned the second. 25-10 MCF5282 User’s Manual MOTOROLA...
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Data should never be written into a receive message buffer. If this is done while a message is being transferred from an SMB, the control/status word will reflect a full or overrun condition, but no interrupt will be requested. MOTOROLA Chapter 25. FlexCAN 25-11...
When transmitting a remote frame, the user initializes a message buffer as a transmit message buffer with the RTR bit set to one. Once this remote frame is transmitted 25-12 MCF5282 User’s Manual MOTOROLA...
FlexCAN module operates like in error passive mode. Since the module does not influence the CAN bus in this mode the host device is capable of functioning like a monitor or for automatic bit-rate detection. MOTOROLA Chapter 25. FlexCAN Functional Overview...
• If during system start-up, only one node is operating, then its TXCTR increases with each message it’s trying to transmit as a result of ACK_ERROR. A transition to bus state Error Passive should be executed as described, while this device never enters the Bus_Off state. MOTOROLA Chapter 25. FlexCAN Functional Overview 25-15...
In both the transmit and receive processes, the first action in preparing a message buffer should be to deactivate the buffer by setting its code field to the proper value. This requirement is mandatory to assure data coherency. 25-16 NOTE MCF5282 User’s Manual MOTOROLA...
• The FlexCAN ignores its Rx pins and drives its Tx pins as recessive. • The FlexCAN loses synchronization with the CAN bus, and the STOPACK and NOTRDY bits in the module configuration register are set. MOTOROLA Chapter 25. FlexCAN Functional Overview...
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• To prevent old frames from being sent when the FlexCAN awakes from low-power stop mode via the self-wake mechanism, disable all transmit sources, including transmit buffers configured for remote request responses, before placing the FlexCAN in low-power stop mode. 25-18 MCF5282 User’s Manual MOTOROLA...
IMASK bit is set. There is no distinction between Tx and Rx interrupts for a particular buffer, under the assumption that the buffer is initialized for either transmission or reception, and thus its MOTOROLA Chapter 25. FlexCAN Functional Overview...
FlexCAN prescaler is enabled. This is a read-only bit. 0 The FlexCAN has exited debug mode and the prescaler is enabled. 1 The FlexCAN has entered debug mode, and the prescaler is disabled. MOTOROLA Description Chapter 25. FlexCAN Programmer’s Model...
PSEG2 PSEG2 — Phase Buffer Segment 2. The PSEG2 field defines the length of phase buffer segment 2 in the bit time. The valid programmed values are 0 through 7. The length of phase buffer segment 2 is calculated as follows: Phase Buffer Segment 2 = (PSEG2 + 1) Time Quanta MOTOROLA Description f sys S-clock...
FCS[1:0] bits will again reflect the bus off state. Refer to Section 25.5.11, “FlexCAN Receive Error Counter (RXECTR)” for more information on entry into and exit from the various fault confinement states. 00 Error active 01 Error passive 1X Reserved MOTOROLA Description Chapter 25. FlexCAN Programmer’s Model 25-29...
CPU reads the flag as a one and writes the flag as a zero, the flag is not cleared. This register can be written to zeros only. 0 The interrupt for the corresponding buffer is disabled. 1 The interrupt for the corresponding buffer is enabled. MOTOROLA Description BUF13I BUF1I...
TXECTR Transmit error counter. Indicates the current transmit error count as defined in the CAN protocol. See Section 25.4.9, “FlexCAN Error Counters” for more details. 25-32 RXECTR 0000_0000 IPSBAR + 0x1C_0026 Description TXECTR 0000_0000 IPSBAR + 0x1C_0028 Description MCF5282 User’s Manual MOTOROLA...
The digital I/O pins on the MCF5282 are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pins. Figure 26-1 is a block diagram of the MCF5282 ports. MOTOROLA Chapter 26. General Purpose I/O Module 26-1...
• Master mode Ports A and B function as the upper external data bus. Ports C and D can function as the lower external data bus. Ports E–J are configured to support external memory. MOTOROLA Chapter 26. General Purpose I/O Module Introduction...
UART0 receive serial data / Port UA[1] — — UART0 transmit serial data / Port UA[0] 23–16 Port Output Data Registers PORTB PORTC PORTF PORTG PORTDD PORTEH PORTQS PORTSD PORTUA MCF5282 User’s Manual Description 15–8 7–0 PORTD PORTH PORTEL PORTTC Reserved MOTOROLA Access...
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S/U = supervisor or user mode access. User mode accesses to supervisor-only addresses have no effect and cause a cycle termination transfer error. Writing to reserved address locations has no effect and reading returns 0s. MOTOROLA 23–16 15–8 Port Data Direction Registers...
Port n data direction bits. 1 Port n pin configured as an output 0 Port n pin configured as an input — Reserved, should be cleared. MCF5282 User’s Manual DDRn2 DDRn1 DDRn0 DDRn2 DDRn1 DDRn0 DDRn2 DDRn1 DDRn0 Description MOTOROLA...
(write) 0 Port x pin state is 0 (read) — Reserved, should be cleared. CLRn5 CLRn4 CLRn3 0000_0000 (CLRDD), 0x10_0046 (CLREH), 0x10_0047 (CLREL) MCF5282 User’s Manual PORTnP2/ PORTnP1/ PORTnP0/ SETn2 SETn1 SETn0 Current Pin State Description CLRn2 CLRn1 CLRn0 MOTOROLA...
1 Port C,D pins configured for primary function (D[15:8], D[7:0]) 0 Port C,D pins configured for digital I/O Reserved, should be cleared. Port Size of PBPA Reset External Boot Value Device 8-bit 16-bit 32-bit MCF5282 User’s Manual PCDPA Reset Value MOTOROLA...
Reset state determined during reset configuration as shown in Table 26-10. Table 26-9. PEPAR Field Descriptions Bits Name PEPA7 PEPA6 PEPA5 PEPA4 MOTOROLA Chapter 26. General Purpose I/O Module — PEPA6 — See Note 1 — PEPA2 See Note 1...
0x Port E0 pin configured for digital I/O 10 Port E0 pin configured for alternate function (SYNCB) 11 Port E0 pin configured for primary function (TIP) Reset Values for Reset Values for PEPAn Bits (n = PEPAn Fields 2,3,4,5,6,7) (n = 0,1) MCF5282 User’s Manual MOTOROLA...
Name PFPA7 PFPA6 PFPA5 4–0 — MOTOROLA Chapter 26. General Purpose I/O Module PFPA5 IPSBAR + 0x10_0051 Description Port F pin assignment 1. The PFPA7 bit configures the port F7 pin for its primary function (A23), alternate function (CS6), or digital I/O.
Port J pin assignment 0. This bit configures the port J0 pin for its primary function (CS0) or digital I/O. 1 Port J0 pin configured for its primary function (CS0) 0 Port J0 pin configured for digital I/O MCF5282 User’s Manual PJPA2 PJPA1 PJPA0 MOTOROLA...
R/W: Field PASPA3 Reset R/W: Address Figure 26-23. Port AS Pin Assignment Register (PASPAR) MOTOROLA Chapter 26. General Purpose I/O Module — 000_0000 IPSBAR + 0x10_0055 Description Port SD pin assignment. This bit configures the port SD[5:0] pins for their primary functions (SRAS, SCAS, DRAMW, SDRAM_CS[1:0], SCKE) or digital I/O.
(SCL), alternate function (UTXD2), or digital I/O. 0x Port AS0 pin configured for digital I/0 10 Port AS0 pin configured for alternate function (UTXD2) 11 Port AS0 pin configured for primary function (SCL) — 0000_0000 IPSBAR + 0x10_0058 MCF5282 User’s Manual MOTOROLA...
Name — PQSPA6 PQSPA5 PQSPA4 PQSPA3 MOTOROLA Chapter 26. General Purpose I/O Module Description Port EH pin assignment. This bit configures the port EH pins for its primary functions (ETXCLK, ETXEN, ETXD[0], ECOL, ERXCLK, ERXDV, ERXD[0], ECRS) or digital I/O.
00 Port TC2 pin configured for digital I/O 01 Port TC2 pin configured for alternate 2 function (URTS0) 10 Port TC2 pin configured for alternate 1 function (URTS1) 11 Port TC2 pin configured for primary function (DTOUT3) MCF5282 User’s Manual PTCPA0 MOTOROLA...
Bits Name 7–6 PTDPA3 PTDPA2 MOTOROLA Chapter 26. General Purpose I/O Module Description Port TC pin assignment 1. This field configures the port TC1 pin for its primary function (DTIN2), alternate 1 function (UCTS1), alternate 2 function (UCTS0) or digital I/O.
Port UA pin assignment 0. This bit configures the port UA0 pin for its primary function (UTXD0) or digital I/O. 1 Port UA0 pin configured for primary function (UTXD0) 0 Port UA0 pin configured for digital I/O MCF5282 User’s Manual PUAPA2 PUAPA1 PUAPA0 MOTOROLA...
Input data on all pins configured as digital I/O is synchronized to the rising edge of CLKOUT, as shown in Figure 26-29. CLKOUT INPUT REGISTER PIN DATA Figure 26-29. Digital Input Timing MOTOROLA Chapter 26. General Purpose I/O Module 26-25...
A/D conversion • Subqueues possible using pause mechanism • Queue complete and pause interrupts available on both queues • Queue pointers indicating current location for each queue • Automated queue modes initiated by: MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) 27-1...
(18 with External MUXing) Reference Inputs Analog Input MUX and Digital Signal Functions Analog-to-Digital Converter 64-Entry Queue of 10-bit 64-Entry Table Conversion of 10-bit Command Words Results (CCWs) 10-bit to 16-bit Result Alignment MCF5282 User’s Manual Analog Power Inputs 10-bit MOTOROLA...
The QADC enters a low-power idle state whenever the QSTOP bit is set or the CPU enters low-power stop mode. QADC stop: • Disables the analog-to-digital converter, effectively turning off the analog circuit MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) Modes of Operation 27-3...
The four port QA signals can be used as analog inputs or as a bidirectional 4-bit digital input/output port. 27.4.1.1 Port QA Analog Input Signals When used as analog inputs, the four port QA signals are referred to as AN[56:55, 53:52]. 27-4 ) to stabilize the analog circuits. MCF5282 User’s Manual MOTOROLA...
The four port QB signals can be used as analog inputs or as a 4-bit digital I/O port. 27.4.2.1 Port QB Analog Input Signals When used as analog inputs, the four port QB signals are referred to as AN[3:0]. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) AN0/ANW/PQB0...
DDRQA is ignored. 27.4.5 Multiplexed Analog Input Signals In external multiplexed mode, four of the port QB signals are redefined so that each represent four analog input channels. See Table 27-1. 27-6 MCF5282 User’s Manual MOTOROLA...
64 half-word entries are the result table which occupies 192 half-word address locations because the result data is readable in three data alignment formats. Table 27-2 is the QADC memory map. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) Channels...
QADC Status Register 0 (QASR0) QADC Status Register 1 (QASR1) Reserved Conversion Command Word Table (CCW) Right Justified, Unsigned Result Register (RJURR) Left Justified, Signed Result Register (LJSRR) Left Justified, Unsigned Result Register (LJURR) 0000_0000 MCF5282 User’s Manual Access — — — MOTOROLA...
Port QB signals are referred to as PQB[3:0] when used as a 4-bit, digital input-only port. Port QB can also be used for non-multiplexed (AN[3:0]) and multiplexed (ANZ, ANY, ANX, ANW) analog inputs. PORTQA and PORTQB are not initialized by reset. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) — 1000_0000...
Typically, these bits are written once when the QADC is initialized and not changed thereafter. The bits in this register are read anytime, write anytime (except during stop mode). MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) NOTE...
The prescaler should be selected so that the QADC clock rate is within the required f range. See MCF5282 Electrical Characteristics. 27-12 — 0000_0000 QPR5 QPR4 QPR3 0001_0011 IPSBAR + 0x19_000a, 0x19_000b Description QCLK MCF5282 User’s Manual — QPR2 QPR1 QPR0 2(QPR[6:0] + 1) QCLK MOTOROLA...
Selects the operating mode for queue 1. Table 27-7 shows the bits in the MQ1 field which enable different queue 1 operating modes. 7–0 — Reserved, should be cleared. 27-14 SSE1 MQ112 MQ111 0000_0000 — 0000_0000 IPSBAR + 0x19_000c, 0x19_000d Description MCF5282 User’s Manual MQ110 MQ19 MQ18 MOTOROLA...
11100 Periodic timer continuous-scan mode: time = QCLK period × 2 11101 Periodic timer continuous-scan mode: time = QCLK period × 2 11110 11111 Externally gated continuous-scan mode MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) Register Descriptions Operating Mode 27-15...
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CCW16. When the pause software interrupt occurs again, BQ2 can be changed back to CCW10. After the end-of-queue is recognized in CCW39, an internal retrigger event is created and execution now restarts at CCW10. 27-16 MCF5282 User’s Manual MOTOROLA...
Interval timer single-scan mode: time = QCLK period x 2 01001 Interval timer single-scan mode: time = QCLK period x 2 01010 Interval timer single-scan mode: time = QCLK period x 2 27-18 Description Operating Modes MCF5282 User’s Manual MOTOROLA...
The end of a queue is identified in the following cases: • When execution is complete on the CCW in the location prior to the one pointed to by BQ2 MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) Register Descriptions Operating Modes...
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In externally gated continuous-scan mode, the behavior of TORn has been redefined. In the case that the queue reaches an end-of-queue condition for the second time during an open 27-20 NOTE: MCF5282 User’s Manual MOTOROLA...
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• Queue 1 paused with queue 2 trigger pending Figure 27-12 displays the status conditions of the QS field as the QADC goes through the transition from queue 1 active to queue 2 active. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) Register Descriptions...
1 Amplifier bypass mode enabled 0 Amplifier bypass mode disabled NOTE: BYP is maintained for software compatibility but has no functional benefit on this version of the QADC. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) — 0000_00 CHAN5...
Reserved, should be cleared. 27.6.8.3 Left-Justified Unsigned Result Register (LJURR) Field Reset R/W: 27-30 Description RESULT Undefined RESULT Undefined IPSBAR + 0x19_0300, 0x19_037e Description ), the signed equivalent in this register would be 0x8000, RESULT Undefined MCF5282 User’s Manual ), the signed MOTOROLA...
This minimizes the number of analog signals that need to be shielded due to the proximity of noisy high speed digital signals at the microcontroller chip. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) —...
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MA[1:0], to select one of four inputs. These inputs are connected to all four external multiplexer chips. The analog output of the four multiplexer chips are each connected to separate QADC inputs (ANW, ANX, ANY, and ANZ) as shown in Figure 27-18 27-32 MCF5282 User’s Manual MOTOROLA...
CCW. The QADC also converts the proper input channel (ANW, ANX, ANY, and ANZ) by interpreting the CCW channel number. As a result, up to 16 externally multiplexed channels appear to the conversion queues as MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) AN0/ANW/PQB0...
Figure 27-19 shows a block diagram of the QADC analog subsystem. 27-34 Number of Analog Input Channels Available Two External Three External Muxes 4 + 8 = 12 3 + 12 = 15 MCF5282 User’s Manual 1, 2 Four External Muxes Muxes 2 + 16 = 18 MOTOROLA...
A conversion requires a minimum of 14 QCLK cycles (7 µs with a 2.0-MHz QCLK). If the maximum final sample time period of 16 QCLKs is selected, the total conversion time is 28 QCLKs or 14 µs (with a 2.0-MHz QCLK). MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) 16:1...
QACR1 and QACR2. Once a queue has been started by a trigger event (any of the ways to cause the QADC to begin executing the CCWs in a queue or subqueue), the QADC performs a sequence of conversions and places the results in the result word table. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) 27-37...
1, and there are six subqueues within queue 1, a separate rising edge is required on the external trigger signal after every pause to begin the execution of each subqueue (refer to Figure 27-22). 27-38 MCF5282 User’s Manual MOTOROLA...
QASR0, and a pause interrupt may be requested. The status of the queue is shown to be paused, indicating completion of a subqueue. The QADC then waits for another trigger event to again begin execution of the next subqueue. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) Digital Control Subsystem Result Word Table •...
Set when a queue completes execution up through a pause bit Trigger overrun Set when a new trigger event occurs before the queue is finished servicing the error (TOR) previous trigger event 27-40 NOTE Table 27-22. Trigger Events Events Table 27-23. Status Bits Function MCF5282 User’s Manual MOTOROLA...
After the queue is complete, the first newly detected trigger event causes queue execution to begin again. When the trigger event rate is high, a new trigger event can be seen very soon after completion of the previous queue, MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) TOR1...
1 execution can begin. Queue 2 is considered suspended. After queue 1 is finished, queue 2 starts over with the first CCW, MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) ACTIVE...
CCW, not the first CCW, in the queue. 27-44 ACTIVE PAUSE ACTIVE ACTIVE ACTIVE SUSPEND 1000 0100 0110 1010 ACTIVE PAUSE ACTIVE PAUSE SUSPEND 1010 0110 0101 0110 MCF5282 User’s Manual RESUME = 0 IDLE ACTIVE IDLE 0010 0000 ACTIVE IDLE ACTIVE IDLE 1010 0010 0000 MOTOROLA...
2 were being executed when a new trigger event occurs. Trigger overrun on queue 2 thus allows the user to know that queue 1 is taking up so much QADC time that queue 2 trigger events are being lost. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) ACTIVE...
Examples of this situation are: • The pause bit is set in CCW10 and EOQ is programmed into CCW10. • During queue 1 operation, the pause bit set in CCW32, which is also BQ2. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) Digital Control Subsystem...
A single-scan queue operating mode is used to execute a single pass through a sequence of conversions defined by a queue. By programming the MQ1 field in QACR1 or the MQ2 field in QACR2, these modes can be selected: • Software-initiated single-scan mode • Externally triggered single-scan mode 27-50 MCF5282 User’s Manual MOTOROLA...
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Software can initiate the execution of a scan sequence for queue 1 or 2 by selecting software-initiated single-scan mode and writing the single-scan enable bit in QACR1 or QACR2. A trigger event is generated internally and the QADC immediately begins MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) Digital Control Subsystem...
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Queue scan must be enabled by setting the single-scan enable bit for queue 1. If a pause is encountered, the pause flag does not set, and execution continues without pausing. 27-52 MCF5282 User’s Manual MOTOROLA...
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The interval timer single-scan mode can be used in applications that need coherent results. For example: • When it is necessary that all samples are guaranteed to be taken during the same scan of the analog signals MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) 27-53...
The next trigger event causes queue execution to begin again, starting with the first CCW in the queue. 27-54 NOTE MCF5282 User’s Manual MOTOROLA...
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Interrupts are normally not used with the software-initiated continuous-scan mode. Rather, the latest conversion results can be read from the result table at any time. Once initiated, software action is not needed to sustain conversions of channel. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) Digital Control Subsystem...
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1 is always the first CCW in the CCW table. The condition of the gate is only sampled after each conversion during queue execution, so closing the gate for a period less than a conversion time interval does not guarantee the closure will be captured. 27-56 MCF5282 User’s Manual MOTOROLA...
Before using the QADC, the prescaler must be initialized with values that put the QCLK within the specified range. Though most applications initialize the prescaler once and do not change it, write operations to the prescaler fields are permitted. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) 27-57...
• System reset is asserted. • Stop mode is enabled. • Debug mode is enabled. 27-58 QPR[6:0] Prescaler ATD Converter State Machine Binary Counter Periodic Timer/Interval Timer Select CAUTION MCF5282 User’s Manual SAR Control Periodic/Interval Trigger Event for Q1 and Q2 MOTOROLA...
To dedicate the entire CCW table to queue 2, place queue 1 in disabled mode and set BQ2 to the first location in the CCW table (CCW0). Figure 27-43 illustrates the operation of the queue structure. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) Digital Control Subsystem...
0 0 0 0 0 Right-Justified, Unsigned Result [15:6] RESULT Left-Justified, Signed Result [15:6] RESULT Left-Justified, Unsigned Result MCF5282 User’s Manual • • • • • • [9:0] RESULT [5:0] 0 0 0 0 0 [5:0] 0 0 0 0 0 MOTOROLA...
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1 can prevent completion of queue 2. If this occurs, execution of queue 2 can begin with the aborted CCW entry (RESUME = 1). MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) Digital Control Subsystem...
All write operations to the result word table are right justified. 27.9 Signal Connection Considerations The QADC requires accurate, noise-free input signals for proper operation. This section discusses the design of external circuitry to maximize QADC performance. 27-62 NOTE MCF5282 User’s Manual MOTOROLA...
V amplifier has accurately transferred the input signal, resolution is ratiometric within the limits defined by V and V MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) , should be low-pass filtered from its source to obtain a and V...
10 mV lower than V , resulting in a minimum obtainable 10-bit conversion value .020 .030 5.100 5.110 Inputs in Volts (V = 5.120 V, V MCF5282 User’s Manual , the sample amplifier can never . This results 5.120 5.130 = 0 V) MOTOROLA...
• Externally gated single scan mode for Q1 • Single scan enable bit (SSE1) is set. When the gate closes and opens again, the conversions start with the first CCW in Q1. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) TIME BETWEEN...
(or in standalone analog systems). Close attention must be paid not to introduce additional sources of noise into the analog circuitry. Common sources of noise include ground loops, inductive coupling, and combining digital and analog grounds together inappropriately. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) CCW1 CCW2...
+5 V AGND QADC Figure 27-49. Star-Ground at the Point of Power Supply Origin Other suggestions for PCB layout in which the QADC is employed include: 27-68 NOTE Digital Power Supply +5 V PGND MCF5282 User’s Manual +5 V MOTOROLA...
Figure 27-51 shows positive stress conditions can activate a similar PNP transistor. Figure 27-50. Input Signal Subjected to Negative Stress MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) or less than V applied to an analog input which cause...
) under negative or positive stress is determined by INJN INJP – – Stress I INJN -------------------------------------------- - R Stress – – Stress ------------------------------------------------------------- INJP Stress ‹‹ 1). The I can be expressed by this equation: MCF5282 User’s Manual (current coupling ratio) MOTOROLA...
QADC analog input signal through a separate multiplexer chip. Also, an example of an analog signal source connected directly to a QADC analog input channel is displayed. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) 27-71...
C Filter C MUXIN C Filter C MUXIN C Filter C MUXIN Notes: C Filter 1. Typical Value 2. R , Typically 10 kΩ–20 kΩ Filter MCF5282 User’s Manual Interconnect QADC C SAMP C PCB SAMP C SAMP C PCB MOTOROLA...
QADC and the user's external circuitry. This circuitry is assumed to be a simple RC low-pass filter passing a signal from a source to the QADC input signal. These paragraphs make the following assumptions: MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) Internal Circuit Model...
MCF5282 User’s Manual changes in charges, the voltage across to charge to within 1/2 of 10 kΩ 100 kΩ 76 ms 760 ms 7.6 ms 76 ms 760 µs 7.6 ms 76 µs 760 µs 7.6 µs 76 µs MOTOROLA...
(QASR0). In other words, flag bits can be polled to determine when new results are available. Table 27-26 shows the status flag and interrupt enable bits which correspond to queue 1 and queue 2 activity. MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) CAUTION Leakage Value (10-Bit Conversions)
The pause and complete interrupts for queue 1 and queue 2 have separate interrupt vector levels, so that each source can be separately serviced. 27-76 Queue Activity MCF5282 User’s Manual Status Interrupt Flag Enable Bit CIE1 PIE1 CIE2 PIE2 MOTOROLA...
• Software-assertable RSTO pin independent of chip reset state • Software-readable status flags indicating the cause of the last reset • LVD control and status bits for setup and use of LVD reset or interrupt MOTOROLA Chapter 28. Reset Controller Module 28-1...
This active-low output signal is driven low when the internal reset controller module resets the chip. When RSTO is active, the user can drive override options on the data bus. 28-2 Reset Controller Input Direction Hysteresis — MCF5282 User’s Manual RSTO To Internal Resets Input Synchronization — MOTOROLA...
1 Assert RSTO pin 0 Negate RSTO pin CAUTION: External logic driving reset configuration data during reset needs to be considered when asserting the RSTO pin when setting FRCRSTOUT. — Reserved, should be cleared. MOTOROLA Bits 7:0 Reserved Reserved — LVDF...
RSR can be read at any time. Writing to RSR has no effect. Field — Reset Address Figure 28-3. Reset Status Register (RSR) 28-4 Description drops below V SOFT Reset Dependent IPSBAR + 0x11_0001 MCF5282 User’s Manual (minimum). The vector for MOTOROLA...
Loss-of-lock reset flag. Indicates that the last reset state was caused by a PLL loss of lock. 1 Last reset caused by a loss of lock 0 Last reset not caused by loss of lock MOTOROLA Description Chapter 28. Reset Controller Module...
PLL clock mode is selected, until the PLL achieves phase lock. Then after approximately another 512 cycles, RSTO is negated and the part begins operation. 28-6 Asynchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Synchronous Asynchronous MCF5282 User’s Manual Type MOTOROLA...
RSTO for approximately 512 cycles. Then the part exits reset and resumes operation. 28.5.1.7 LVD Reset The LVD reset will occur when the supply input voltage, V drops below V (minimum). MOTOROLA Chapter 28. Reset Controller Module 28-7...
The reset logic control flow is shown in Figure 28-4. In this figure, the control state boxes have been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All cycle counts given are approximate. 28-8 MCF5282 User’s Manual MOTOROLA...
LOSS OF CLOCK? LOSS OF LOCK? RSTI PIN OR WD TIMEOUT OR SW RESET? NEGATE RSTO MOTOROLA ENABLE BUS MONITOR BUS CYCLE COMPLETE? ASSERT RSTO AND LATCH RESET STATUS RSTI NEGATED? PLL MODE? WAIT 512 CLKOUT CYCLES RCON ASSERTED? Figure 28-4. Reset Control Flow Chapter 28.
If the external RSTI pin is asserted for at least four rising CLKOUT edges while waiting for PLL lock or the 512 cycles, the external reset is recognized. Reset processing switches to wait for the external RSTI pin to negate (8). 28-10 MCF5282 User’s Manual MOTOROLA...
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For a LVD reset, the LVD bit in the RSR is set, and the SOFT, WDR, EXT, LOC, and LOL bits are cleared to 0 even if another type of reset condition is detected during the reset sequence for LVD. MOTOROLA Chapter 28. Reset Controller Module 28-11...
Debug interrupts let real-time systems execute a unique service routine that can quickly save the contents of key registers and variables and return the system to normal operation. External development MOTOROLA ColdFire CPU Core Debug Module...
29.2 Signal Description Table 29-1 describes debug module signals. All ColdFire debug signals are unidirectional and related to a rising edge of the processor’s clock signal. The standard 26-pin debug connector is shown in Section 29.8, “Motorola-Recommended BDM Pinout.” Signal Development Serial Internally synchronized input.
CSR settings. CSR also controls the number of address bytes displayed, indicated by the PST marker value preceding the DDATA nibble that begins the data output. See Section 29.3.1, “Begin Execution of Taken Branch (PST = 0x5).” 0110 Reserved MOTOROLA Definition Chapter 29. Debug Support Real-Time Trace Support 29-3...
3. The new target address is optionally available on subsequent cycles using the DDATA port. The number of bytes of the target address displayed on this port is configurable (2, 3, or 4 bytes). 29-4 Definition MCF5282 User’s Manual MOTOROLA...
MCF5282 is using the WDEBUG instruction to access debug module registers or the resulting behavior is undefined. These registers, shown in Figure 29-4, are treated as 32-bit quantities, regardless of the number of implemented bits. MOTOROLA default default A[3:0] A[7:4] Chapter 29.
Thus, loading a register to perform a specific function that shares hardware resources is destructive to the shared function. For example, a BDM command to access memory overwrites an address breakpoint in ABHR. A BDM write command overwrites the data breakpoint in DBR. MOTOROLA Abbreviation — AATR PBMR —...
These bits also define the TT encoding for BDM memory commands. In this case, the 01 encoding indicates an external or DMA access (for backward compatibility). These bits affect the TM bits. 29-8 0000_0000_0000_0101 command. WDMREG 0x06 Description MCF5282 User’s Manual MOTOROLA...
BDM port using the ABLR is accessible in supervisor mode as debug control register 0x0D using the WDEBUG instruction and via the BDM port using the WDMREG DRc[4–0] Figure 29-6. Address Breakpoint Registers (ABLR, ABHR) MOTOROLA Description Address — commands. RDMREG WDMREG command.
01 Lower 2 bytes of the target address 10 Lower 3 bytes of the target address 11 Entire 4-byte target address See Section 29.3.1, “Begin Execution of Taken Branch (PST = 0x5).” MOTOROLA Description command, or reading CSR will clear TRG. Chapter 29. Debug Support...
DBMR is accessible in supervisor mode as debug control register 0x0F,using the WDEBUG instruction and via the BDM port using the WDMREG DRc[4–0] Figure 29-8. Data Breakpoint/Mask Registers (DBR/DBMR) 29-12 Description command, the processor executes the next instruction and Data (DBR); Mask (DBMR) Uninitialized commands. WDMREG command. 0x0E (DBR), 0x0F (DBMR) MCF5282 User’s Manual MOTOROLA...
TDR is configured appropriately. PBR bits are masked by setting corresponding PBMR bits. Results are compared with the processor’s program counter register, as defined in TDR. Figure 29-9 shows the PC breakpoint register. MOTOROLA Description Description Access Size...
15–0 define the first-level trigger. 29-14 Program Counter — commands using values shown in Section 29.5.3.3, “Command Set 0x08 Description Mask — via the BDM port using the wdmreg command. 0x09 Description MCF5282 User’s Manual MOTOROLA...
Although most BDM operations can occur in parallel with CPU operations, unrestricted BDM operation requires the CPU to be halted. The sources that can cause the CPU to halt are listed below in order of priority: 29-16 Description MCF5282 User’s Manual MOTOROLA...
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STOP opcode. CSR[27–24] indicates the halt source, showing the highest priority source for multiple halt conditions. MOTOROLA command causes the processor to Chapter 29. Debug Support Background Debug Mode (BDM)
• C2—Second synchronization cycle for DSI (DSCLK is high). • C3—BDM state machine changes state depending upon DSI and whether the entire input data transfer has been transmitted. • C4—DSO changes to next value. 29-18 Current Past MCF5282 User’s Manual Next Next State Current MOTOROLA...
Control. This bit is reserved. Command and data transfers initiated by the development system should clear C. 15–0 Data bits 15–0. Contains the data to be sent from the development system to the debug module. MOTOROLA NOTE: Data Field [15:0]...
- Steal. Command generates bus cycles that can be interleaved with bus accesses. - Parallel. Command is executed in parallel with CPU activity. 0x4 is a three-bit field. Unassigned command opcodes are reserved by Motorola. All unused command formats within any revision level perform a 29-20 Description to dump large blocks of memory.
Operands and addresses are transferred most-significant word first. In the following descriptions of the BDM command set, the optional set of extension words is defined as address, data, or operand data. MOTOROLA Op Size Extension Word(s) Description...
Next Command Code ’NOT READY’ NEXT CMD MS RESULT LS RESULT NEXT CMD BERR ’NOT READY’ Sequence taken if bus error occurs on memory access High- and low-order 16 bits of result in this example). The READ MOTOROLA...
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S = 1 for illegal commands, not-ready responses, and transfers with bus-errors. Section 29.5.2, “BDM Serial Interface,” describes the receive packet format. Motorola reserves unassigned command opcodes for future expansion. Unused command formats in any revision level perform a 29.5.3.3.1 Read A/D Register ( Read the selected address or data register and return the 32-bit result.
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29-24 WAREG WDREG D[31:16] D[15:0] Command Format WAREG WDREG MS DATA LS DATA ’NOT READY’ ’NOT READY’ NEXT CMD BERR ’NOT READY’ Command Sequence WAREG WDREG READ MCF5282 User’s Manual Register NEXT CMD ’CMD COMPLETE’ MOTOROLA...
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Word results return 16 bits of data; longword results return 32. Bytes are returned in the LSB of a word result; the upper byte is undefined. 0x0001 (S = 1) is returned if a bus error occurs. MOTOROLA A[31:16] A[15:0]...
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(1, 2, or 4) and saved in a temporary register. Subsequent use this address, perform the memory read, increment it by the current operand size, and store the updated address in the temporary register. MOTOROLA DATA LS ADDR ’NOT READY’...
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Command/Result Formats: Byte Command Result Word Command Result Longword Command Result Figure 29-25. 29-28 NOTE: , or another READ command is processed, allowing the operand DUMP D[15:0] D[31:16] D[15:0] Command/Result Formats DUMP MCF5282 User’s Manual command. DUMP D[7:0] MOTOROLA...
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FILL a valid command only when preceded by another or a command. Otherwise, an illegal command response WRITE is returned. The padding without corrupting the address pointer. MOTOROLA READ MEMORY LOCATION NEXT CMD ’NOT READY’ READ MEMORY...
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NEXT CMD ’NOT READY’ WRITE MEMORY LOCATION NEXT CMD ’NOT READY’ Command Sequence FILL MCF5282 User’s Manual D[7:0] ’NOT READY’ NEXT CMD ’CMD COMPLETE’ NEXT CMD BERR ’NOT READY’ ’NOT READY’ NEXT CMD ’CMD COMPLETE’ NEXT CMD BERR ’NOT READY’ MOTOROLA...
Figure 29-31. Command Sequence: Figure 29-32. Operand Data: None Result Data: The command-complete response, 0xFFFF (with S cleared), is returned during the next shift operation. MOTOROLA Command Format NEXT CMD ’CMD COMPLETE’ Command Sequence Command Format NEXT CMD ’CMD COMPLETE’...
MAC Accumulator 0,1 Extension Bytes (ACCEXT01) MAC Accumulator 2,3 Extension Bytes (ACCEXT23) MAC Accumulator 1 (ACC1) MAC Accumulator 2 (ACC2) MAC Accumulator 3 (ACC3) Status Register (SR) Program Register (PC) Flash Base Address Register 0 (FLASHBAR) RAM Base Address Register (RAMBAR) MCF5282 User’s Manual MOTOROLA...
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BDM-initiated reads and writes of its programming model. In particular, it is necessary that any result rounding modes be disabled during the read/write process so the exact bit-wise contents of the EMAC registers are accessed. MOTOROLA READ MS ADDR CONTROL ’NOT READY’...
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// read macsr contents & save // disable all rounding modes // read the desired accumulator // read macsr contents & save // disable all rounding modes // write the desired accumulator WCREG D[31:16] D[15:0] Command/Result Formats WCREG MCF5282 User’s Manual MOTOROLA...
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Command/Result Formats: Command Result Figure 29-37. Table 29-20 shows the definition of DRc encoding. MOTOROLA MS ADDR MS DATA ’NOT READY’ ’NOT READY’ LS DATA ’NOT READY’...
WDMREG MS DATA LS DATA ’NOT READY’ ’NOT READY’ NEXT CMD ’ILLEGAL’ ’NOT READY’ Command Sequence WDMREG MCF5282 User’s Manual Initial State Page p. 29-10 — — NEXT CMD LS RESULT NEXT CMD ’NOT READY’ NEXT CMD ’CMD COMPLETE’ MOTOROLA...
TDR. PC breakpoints are treated in a precise manner—exception recognition and processing are initiated before the excepting instruction is executed. All other breakpoint events are MOTOROLA Breakpoint Status No breakpoints enabled...
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RSTI is negated and the processor begins reset exception processing. It can be set while the processor is halted before reset exception processing begins. See Section 29.5.1, “CPU Halt.” • A debug interrupt always puts the processor in emulation mode when debug interrupt exception processing begins. 29-38 MCF5282 User’s Manual MOTOROLA...
The processor grants the internal bus if these loops are forced across two longwords. MOTOROLA Chapter 29. Debug Support Real-Time Debug Support 29-39...
30.2 Modes of Operation The CCM configures the chip for two modes of operation: • Master mode • Single-chip mode The operating mode is determined at reset and cannot be changed thereafter. MOTOROLA Chapter 30. Chip Configuration Module (CCM) 30-1...
• The chip configuration register (CCR) controls the main chip configuration. • The reset configuration register (RCON) indicates the default chip configuration. • The chip identification register (CIR) contains a unique part number. MOTOROLA Chapter 30. Chip Configuration Module (CCM) Table 30-1. Signal Properties...
(immediately after reset) to lock out test features. Setting any bits in the CCR may lead to unpredictable results. 30-4 Configuration Read-always Write-always Write-once Write-once Bits 31–16 Low-Power Control Register (LPCR) Reserved Unimplemented NOTE MCF5282 User’s Manual Read/Write Access Bits 15–0 Chip Identification Register (CIR) MOTOROLA Access —...
PST[3:0]/DDATA[3:0] enable. This read/write bit enables the Processor Status (PST) and Debug Data (DDATA)n functions of the external pins. 0 PST/DDATA function disabled. 1 PST/DDATA function enabled. — Reserved, should be cleared. MOTOROLA Chapter 30. Chip Configuration Module (CCM) MODE — SZEN PSTEN See Note...
The default PLL mode can be overridden during reset configuration. If the default is overridden, the clock module’s SYNSR[PLLSEL] bit reflects the PLL mode. 30-6 Description RPLLSEL RPLLREF RLOAD 0000_0000_1110_0000 IPSBAR + 0x11_0008 Table 30-5. RCON Field Descriptions Description MCF5282 User’s Manual BOOTPS BOOTSEL — MODE MOTOROLA...
Table 30-6. RCSC Chip Select Configuration This is the value used for the MCF5282. Table 30-7. BOOTPS Port Size Configuration BOOTPS[1:0] This is the value used for the MCF5282. MOTOROLA Chapter 30. Chip Configuration Module (CCM) Description RCSC Chip Select Configuration...
Part identification number. Contains a unique identification number for the device. Part revision number. This number is increased by one for each new full-layer mask set of this part. The revision numbers are assigned in chronological order. MCF5282 User’s Manual MOTOROLA...
Table 30-10. Configuration During Reset Pin(s) Affected Configuration D[31:0], R/W, TA, TEA, TSIZ[1:0], TS, TIP, OE, A[23:0], BS[3:0], CS[3:0] RCON[4:3] = 00 All output pins MOTOROLA Chapter 30. Chip Configuration Module (CCM) Function Digital I/O or primary Input function RCON function for all Input...
The clock mode is selected during reset and reflected in the PLLMODE, PLLSEL, and PLLREF bits of SYNSR. Once reset is exited, the clock mode cannot be changed. Table 30-13 summarizes clock mode selection during reset configuration. MOTOROLA Chapter 30. Chip Configuration Module (CCM) CCR Register MODE Field...
“Memory Map and Registers.” The CCM controls chip configuration at reset as described in Section 30.6, “Functional Description.” 30.8 Interrupts The CCM does not generate interrupt requests. 30-12 Table 30-13. Clock Mode Selection Synthesizer Status Register (SYNSR) PLLSEL Bit MCF5282 User’s Manual PLLREF Bit PLLMOD MOTOROLA...
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This architecture provides access to all data and chip control pins from the board-edge connector through the standard four-pin test access port (TAP) and the JTAG reset pin, TRST. Figure 31-1 shows the block diagram of the JTAG module. MOTOROLA Chapter 31. IEEE 1149.1 Test Access Port (JTAG) 31-1...
• Samples the system pins during operation and transparently shift out the result • Selects between JTAG TAP controller and Background Debug Module (BDM) using a dedicated JTAG_EN pin 31-2 Disable DSCLK Force BKPT = 1 to Debug Module Figure 31-1. JTAG Block Diagram MCF5282 User’s Manual TDO/DSO BKPT DSCLK MOTOROLA...
When one module is selected, the inputs into the other module are disabled or forced to a known logic level as shown in Table 31-3, in order to disable the corresponding module. MOTOROLA Chapter 31. IEEE 1149.1 Test Access Port (JTAG) Table 31-1.
The IDCODE is a read-only register; its value is chip dependent. For more information, see Section 31.5.3.2, “IDCODE Instruction.” Field PRN[[3:0] Reset PRN[3] PRN[2] PRN[1] PRN[0] Field PIN[9:0] Reset MOTOROLA Chapter 31. IEEE 1149.1 Test Access Port (JTAG) DC[5:0] 0111_01 Read only JEDEC[10] 0000_0000_0000_0000 Read only Figure 31-2.
Part identification number. Indicate the device number. 11–1 JEDEC Joint electron device engineering council ID bits. Indicate the reduced JEDEC ID for Motorola. IDCODE register ID. This bit is set to 1 to identify the register as the IDCODE register and not the bypass register according to the IEEE standard 1149.1.
As Figure 31-3 shows, holding TMS at logic 1 while clocking TCLK through at least five rising edges also causes the state machine to enter the test-logic-reset state, whatever the initial state. MOTOROLA Chapter 31. IEEE 1149.1 Test Access Port (JTAG) 31-7...
Selects boundary scan register while applying fixed values to output pins and asserting functional reset Selects IDCODE register for shift Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation MCF5282 User’s Manual SELECT IR-SCAN CAPTURE-IR SHIFT-IR EXIT1-IR PAUSE-IR EXIT2-IR UPDATE-IR MOTOROLA...
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Instruction for manufacturing purposes only TRST pin assertion or power-on reset is required to exit this instruction. Motorola reserves the right to change the decoding of the unused opcodes in the future. 31.5.3.1 External Test Instruction (EXTEST) The EXTEST instruction selects the boundary scan register. It forces all output pins and bidirectional pins configured as outputs to the values preloaded with the SAMPLE/PRELOAD instruction and held in the boundary scan update registers.
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If a user inadvertently enables security on a MCU, the LOCKOUT_RECOVERY instruction allows the disabling of security by the complete erasure of the internal flash contents including the configuration field. This does not compromise security as the entire 31-10 NOTE MCF5282 User’s Manual MOTOROLA...
However, the system clock is not synchronized to TCLK internally. Any mixed operation using both the test logic and the system functional logic requires external synchronization. MOTOROLA Chapter 31. IEEE 1149.1 Test Access Port (JTAG) 31-11...
TRST could be connected to ground. However, since there is a pull-up on TRST, some amount of current results. The internal power-on reset input initializes the TAP controller to the test-logic-reset state on power-up without asserting TRST. 31-12 MCF5282 User’s Manual MOTOROLA...
Chapter 32 Mechanical Data This chapter contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF5282. MOTOROLA Chapter 32. Mechanical Data 32-1...
Flash Memory Program / Erase Supply Voltage Analog Supply Voltage Analog Reference Supply Voltage Analog ESD Protection Voltage Digital Input Voltage Analog Input Voltage EXTAL pin voltage XTAL pin voltage MOTOROLA NOTE: Symbol DDPLL STBY EXTAL XTAL Chapter 33. Electrical Characteristics...
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– 65 to 150 2000 and V range during instantaneous and and could result in external power supply going load will shunt current greater than maximum injection range during MCF5282 User’s Manual Unit °C °C > V ) is greater than MOTOROLA...
Ψ parameters are simulated in accordance with EIA/JESD Standard 51-2 for natural convection. Motorola recommends the use of θ junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer’s system...
= 0 V SSPLL Symbol Max. STBY - 0.3 V STBY - 0.3 V MCF5282 User’s Manual Unit 0.7 x V 5.25 – 0.3 0.35 x V 0.06 x — µA -1.0 µA -1.0 - 0.5 µA -130 — — MOTOROLA...
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QADC pins are at 50pF drive strength. Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load. Programming and erasing all 8 blocks of the Flash. MOTOROLA = 0 V SSPLL Symbol...
= 5.0 V 0.5V, V = 2.7-3.6V, V Parameter Analog Supply Differential Voltage Reference Voltage Low Reference Voltage High Differential Voltage MOTOROLA and V and variation in crystal oscillator frequency DDPLL SSPLL max. Symbol – V – V – V –...
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0.7 (V VDDH-0.8 ≤ V ≤ V ≤ V ≤ V INDC MCF5282 User’s Manual (Continued) Unit –0.3 + 0.3 + 0.3 – 0.3 0.4(V — — — — µA — 10.0 — µA — — -200 — — — MOTOROLA...
Table 33-8. SGFM Flash Program and Erase Characteristics Parameter System clock (read only) System clock (program/erase) is defined to be –40°C and T Refer to the Flash section for more information MOTOROLA = 2.7-3.6V and V = 0 V temperature range, f = 16 MHz)
= 2.7 to 3.6 V) before failure NOTE: Characteristic Control Inputs Data Inputs MCF5282 User’s Manual Symbol Value Unit 10,000 Cycles Retention Years Symbol Unit 12.5 — — CVCH — BKVCH — CHCII — BKNCH — DIVCH — CHDII MOTOROLA...
CLKOUT high to chip selects valid CLKOUT high to byte enables (BS[3:0]) valid CLKOUT high to output enable (OE) valid CLKOUT high to control output (BS[3:0], OE) invalid CLKOUT high to chip selects invalid MOTOROLA Processor Bus Output Timing Specifications 1.5V SETUP HOLD Invalid 1.5V Valid...
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Read/write bus timings listed in Table 33-11 are shown in Figure 33-2, Figure 33-3, and Figure 33-4. 33-12 Symbol Address and Attribute Outputs CHAV CHAI Data Outputs CHDOV CHDOI CHDOZ MCF5282 User’s Manual Unit — — — — — MOTOROLA...
Processor Bus Output Timing Specifications CLKOUT A[23:0] SIZ[1:0] BS[3:0] D[31:0] Figure 33-3. Read Bus Cycle Terminated by TA Figure 33-4 shows a bus cycle terminated by TEA; it displays the timings listed in Table 33-11. 33-14 MCF5282 User’s Manual MOTOROLA...
CLKOUT High to GPIO Output Valid CLKOUT High to GPIO Output Invalid GPIO Input Valid to CLKOUT High CLKOUT High to GPIO Input Invalid MOTOROLA WRITE Figure 33-6. SDRAM Write Cycle Table 33-13. GPIO Timing = 2.7 to 3.6 V, V...
Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time MOTOROLA = 2.7 to 3.6 V, V = 0 V) levels unless otherwise noted. C input timing parameters shown in Figure 33-9.
= 2.4 V to V = 0.5 V) C Input/Output Timings MCF5282 User’s Manual Units — Bus clocks — Bus clocks — — µS — Bus clocks — — Bus clocks — Bus clocks — Bus clocks — Bus clocks MOTOROLA...
ETXCLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs. Refer to the Ethernet chapter for details of this option and how to enable it. MOTOROLA Chapter 33. Electrical Characteristics Fast Ethernet AC Timing Specifications Unit —...
ECOL has the same timing in 10 Mbit 7-wire interface mode. Figure 33-12 shows MII asynchronous input timings listed in Table 33-19. ECRS, ECOL Figure 33-12. MII Async Inputs Timing Diagram 33-22 — MCF5282 User’s Manual Unit — ETXCLK period ETXCLK period Unit — ETXCLK period MOTOROLA...
TRST Setup Time (Negation) to TCLK High JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing TCLK (input) Figure 33-15. Test Clock Input Timing MOTOROLA Chapter 33. Electrical Characteristics JTAG and Boundary Scan Timing Symbol Unit JCYC —...
CLKOUT Rise CLKOUT high to BKPT high Z DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT. MOTOROLA Input Data Valid Figure 33-19. BKPT Timing Characteristic Chapter 33. Electrical Characteristics...
PST[3:0] DDATA[3:0] Figure 33-20. Real-Time Trace AC Timing Figure 33-21 shows BDM serial port AC timing for the values in Table 33-24. CLKOUT DSCLK Current Next Past Current Figure 33-21. BDM Serial Port AC Timing 33-28 MCF5282 User’s Manual MOTOROLA...
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CPU @ 0x809 CPU @ 0x80A CPU @ 0x80B CPU @ 0x80E CPU @ 0x80F CPU @ 0xC04 CPU @ 0xC05 MOTOROLA Name Cache Control Register Access Control Register 0 Access Control Register 1 Other Stack Pointer Vector Base Register...
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IPSBAR + 0x1024 IPSBAR + 0x1040 IPSBAR + 0x1044 IPSBAR + 0x1064 IPSBAR + 0x1084 IPSBAR + 0x10C4 MOTOROLA Name Interrupt Control Register 1-20 Interrupt Control Register 1-21 Interrupt Control Register 1-22 Interrupt Control Register 1-23 Interrupt Control Register 1-24...
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Port EH Output Data Register Port EL Output Data Register MCF5282 User’s Manual Mnemonic Size PALR PAUR IAUR IALR GAUR GALR TFWR FRBR FRSR ERDSR ETDSR EMRBR MIB_RAM PORTA PORTB PORTC PORTD PORTE PORTF PORTG PORTH PORTJ PORTDD PORTEH PORTEL MOTOROLA...
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0x10_001F IPSBAR + 0x10_0020 IPSBAR + 0x10_0021 IPSBAR + 0x10_0022 MOTOROLA Name Port AS Output Data Register Port QS Output Data Register Port SD Output Data Register Port TC Output Data Register Port TD Output Data Register Port UA Output Data Register...
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Port B, C, and D Pin Assignment Register 0x10_0050 IPSBAR + 0x10_0051 IPSBAR + 0x10_0052 MOTOROLA Name Port A Clear Output Data Register Port B Clear Output Data Register Port C Clear Output Data Register Port D Clear Output Data Register...
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Synthesizer Control Register Synthesizer Status Register Edge Port Registers EPORT Pin Assignment Register EPORT Data Direction Register EPORT Interrupt Enable Register MCF5282 User’s Manual Mnemonic Size PJPAR PSDPAR PASPAR PEHLPAR PQSPAR PTCPAR PTDPAR PUAPAR LPCR RCON SYNCR SYNSR EPPAR EPDDR EPIER MOTOROLA...
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0x17_0000 IPSBAR + 0x17_0002 IPSBAR + 0x17_0004 IPSBAR + 0x18_0000 IPSBAR + 0x18_0002 MOTOROLA Name EPORT Data Register EPORT Pin Data Register EPORT Flag Register Watchdog Timer Registers Watchdog Control Register Watchdog Modulus Register Watchdog Count Register Watchdog Service Register...
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(SCM)” for more details. UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software reset command. That is, if channel operation is not disabled, undesirable results may occur. MOTOROLA Name Rx Global Mask Rx Buffer 14 Mask...
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(QSPI_DIN), 14-25 synchronous (QSPI_DOUT), 14-25 reset controller reset in (RSTI), 14-22, 28-2 reset out (RSTO), 28-2 SDRAM controller MCF5282 User’s Manual input/development serial input serial clock , 14-33 , 14-33 , 27-63 SSA) ), 27-63 ), 27-7 serial data output MOTOROLA...
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DMA, see DMA timers general purpose, see general purpose timers programmable interrupt, see programmable inter- rupt timers watchdog, see watchdog timer, 18-2 Timing diagrams MOTOROLA INDEX debug BDM serial port AC timing, 33-28 real-time trace AC timing, 33-28 Ethernet MII async input signal, 33-22...