Motorola MPC860 PowerQUICC User Manual page 619

For the primary rate IDL, the MPC860 supports up to four 8-bit channels in the frame,
determined by the SI RAM programming. Additionally, the MPC860 can assert strobes to
support additional external IDL channels. The IDL interface supports the CCITT I.460
recommendation for data rate adaptation since it separately accesses each bit of the IDL
bus. The current-route RAM speciÞes the bits that are supported by the IDL interface and
the serial controller. The receiver accepts only the bits enabled by the Rx route RAM.
Likewise, the transmitter sends only the bits enabled in the Tx route RAM and three-states
L1TXDx.
21.2.5.2 Programming the IDL Interface
To program the IDL interface, Þrst program SIMODE[GMx] to the IDL grant mode for that
channel. If the receive and transmit sections interface to the same IDL bus, set
SIMODE[CRTx] to internally connect the Rx clock and sync signals to the transmit section.
Then program the SI RAM used for the IDL channels to the preferred routing. See
Section 21.2.3.8, ÒSI RAM Programming Example.Ó
DeÞne the IDL frame structure by programming SIMODE[xFSD] to have a 1-bit delay
from frame sync to data, SIMODE[FE] to sample the sync on the falling edge, and
SIMODE[CE] to transmit on the rising edge of the clock. Program L1TXDx to be
three-stated when inactive via the parallel I/O open-drain register. To support the D channel,
set the appropriate SICR[GR] bit and program the RAM entry to route data to the chosen
SCC. The two deÞnitions of IDL, 8- and 10-bit, are only supported by modifying the SI
RAM programming. In both cases, L1GRx is sampled with L1TSYNCx and transferred to
the D-channel SCC as a grant indication. Repeat the same procedure for an IDL bus on the
second TDM channel.
For example, based on the same 10-bit format as in Section 21.2.3.8, ÒSI RAM
Programming Example,Ó implement an IDL bus using SCC2, SCC3, and SMC2 connected
to the TDM channel as follows:
1. Program both the Rx and Tx sections of the SI RAM as in Table 21-11. Write unused
entries with 0x0001_0000.
Table 21-11. SI RAM Settings for IDL Interface
Entry
Number
SWTR
1 0
2 0
3 0
4 0
5 0
2. SIMODE = 0x8000_0145. Only TDMa is used. SMC2 is connected to the TSA.
MOTOROLA
SSEL CSEL CNT
0000 010 0000
0000 011 0000
0000 000 0000
0000 110 0000
0001 011 0000
Chapter 21. Serial Interface
Part V. The Communications Processor Module
SI RAM
BYT LST
1 0 8 bits SCC2 (B1)
0 0 1 bit SCC3 (D)
0 0 1 bit no support
1 0 8 bits SMC2 (B2)
0 1 1 bit SCC3 (D) and strobe1
Description
21-31