Motorola MPC860 PowerQUICC User Manual page 621

¥ L1CLKOxÑOptional signal; output from the MPC860 for clock devices that do not
interface directly to the GCI. It is 1´ output of L1RCLKx.; otherwise, if the
double-speed clock is used (SIMODE[DSCx] is set), it is L1RCLKx divided by 2.
L1CLK
(2X the Data Rate)
L1SYNC
L1RXD B1
L1TXD B1
Notes: Clock is not to scale.
L1CLKO is not shown.
In addition to the 144-Kbps ISDN 2B+D channels, the GCI provides two channels for
maintenance and control:
¥ B1 is a 64-Kbps bearer channel
¥ B2 is a 64-Kbps bearer channel
¥ M is a 64-Kbps monitor channel
¥ D is a 16-Kbps signaling channel
¥ C/I is a 48-Kbps command/indication channel (includes A and E bits)
The M channel is used to transfer data between layer-1 devices and the control unit (the
core) and the C/I channel is used to control activation/deactivation procedures or to switch
test loops by the control unit. The M and C/I channels of the GCI bus should be routed to
SMC1 or SMC2, which have modes to support the channel protocols. The MPC860 can
support any channel of the GCI bus in the primary rate by modifying the SI RAM
programming.
The GCI supports the CCITT I.460 recommendation as a method for data rate adaptation
since it can access each bit of the GCI separately. The current-route RAM speciÞes which
bits are supported by the interface and serial controller. The receiver accepts only the bits
that are enabled by the SI RAM. The transmitter sends only the bits that are enabled by the
SI RAM and does not drive L1TXDx otherwise. L1TXDx is an open-drain output and
should be pulled high externally.
The MPC860 supports contention detection on the D channel of the SCIT bus. When the
MPC860 has data to send on the D channel, it checks an SCIT bus bit that is marked with
a special route code (usually, bit 4 of C/I channel 2). The physical layer device monitors the
physical layer bus for activity on the D channel and indicates on this bit that the channel is
free. If a collision is detected on the D channel, the physical layer device drives bit 4 of C/I
MOTOROLA
Part V. The Communications Processor Module
B2
B2
Figure 21-27. GCI Bus Signals
Chapter 21. Serial Interface
M (Monitor) D1 D2
M (Monitor) D1 D2
C/I A E
C/I A E
21-33