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Table 16-8 describes MDR.
Bits
Name
0Ð31
MD
Memory data. Contains the RAM array word.
16.4.7 Memory Address Register (MAR)
The memory address register contains an address to be driven on the external bus in the case
of a
command issued to the MCR.
RUN
Bit
0
1
Field
Reset
R/w
Address
Bit
16
17
Field
Reset
R/W
Address
Figure 16-13. Memory Address Register (MAR)
Table 16-9 describes MAR Þelds.
Bits Name
0Ð31 MA
Contains a 32-bit address to be output on the address bus if AMX = 0b11. See Section 16.6.4.1, ÒRAM
Words.Ó
16.4.8 Memory Periodic Timer Prescaler Register (MPTPR)
The memory periodic timer prescaler register (MPTPR) deÞnes the divisor of the external
bus clock used as the memory periodic timer input clock. See Section 15.3, ÒClock
Signals.Ó
Bit
0
1
2
Field
Reset
R/W
Addr
Figure 16-14. Memory Periodic Timer Prescaler Register (MPTPR)
MOTOROLA
Table 16-8. MDR Field Descriptions
2
3
4
5
0000_0000_0000_0000
(IMMR & FFFF0000) + 0x164
18
19
20
21
22
0000_0000_0000_0000
(IMMR & FFFF0000) + 0x166
Table 16-9. MAR Field Description
3
4
5
6
PTP
0000_001x
(IMMR & FFFF0000) + 0x17A
Chapter 16. Memory Controller
Description
6
7
8
9
10
MA
R/W
23
24
25
26
MA
R/W
Description
7
8
9
10
R/W
Part IV. Hardware Interface
11
12
13
14
27
28
29
30
11
12
13
14
Ñ
0000_0000
16-17
15
31
15
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