Input And Output Clocks - Texas Instruments TMS320C6712D User Manual

Floating point digital signal processor
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timing requirements for CLKIN
NO.
1
t c(CLKIN)
Cycle time, CLKIN
2
t w(CLKINH)
Pulse duration, CLKIN high
3
t w(CLKINL)
Pulse duration, CLKIN low
4
t t(CLKIN)
Transition time, CLKIN
† The reference points for the rise and fall transitions are measured at V IL MAX and V IH MIN.
‡ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 25 MHz, use C = 40 ns.
§ See the PLL and PLL Controller section of this data sheet.
CLKIN
switching characteristics over recommended operating conditions for CLKOUT2
(see Figure 22)
NO.
NO.
1
t c(CKO2)
Cycle time, CLKOUT2
2
t w(CKO2H)
Pulse duration, CLKOUT2 high
3
t w(CKO2L)
Pulse duration, CLKOUT2 low
4
t t(CKO2)
Transition time, CLKOUT2
‡ The reference points for the rise and fall transitions are measured at V OL MAX and V OH MIN.
§ C2 = CLKOUT2 period in ns. CLKOUT2 period is determined by the PLL controller output SYSCLK2 period, which must be set to CPU period
divide-by-2.
CLKOUT2
FLOATING POINT DIGITAL SIGNAL PROCESSOR

INPUT AND OUTPUT CLOCKS

†‡§
(see Figure 21)
2
Figure 21. CLKIN Timings
PARAMETER
PARAMETER
2
Figure 22. CLKOUT2 Timings
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
−150
PLL MODE
(PLLEN = 1)
MIN
MAX
6.7
83.3
0.4C
0.4C
5
1
4
3
MIN
C2 − 0.8
(C2/2) − 0.8
(C2/2) − 0.8
1
4
3
4
TMS320C6712D
BYPASS MODE
UNIT
(PLLEN = 0)
MIN
MAX
6.7
ns
0.4C
ns
0.4C
ns
5
ns
4
‡§
−150
UNIT
UNIT
MAX
C2 + 0.8
ns
(C2/2) + 0.8
ns
(C2/2) + 0.8
ns
2
ns
67

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