Architectural Overview; Read This First - Texas Instruments TMS320C28x Reference Manual

About This Manual
This manual describes the central processing unit (CPU) and the assembly language instructions of the
TMS320C28x 32-bit fixed-point digital signal processors (DSPs). It also describes emulation features
available on these DSPs. A summary of the chapters and appendixes follows:
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6

Architectural Overview

This chapter introduces the T320C2800 DSP core that is at the heart of each
TMS320C28x DSP. The chapter includes a memory map and a high-level de-
scription of the memory interface that connects the core with memory and
peripheral devices.
Central Processing Unit
This chapter describes the architecture, registers, and primary functions of
the CPU. The chapter includes detailed descriptions of the flag and control
bits in the most important CPU registers, status registers ST0 and ST1.
Interrupts and Reset
This chapter describes the interrupts and how they are handled by the CPU.
The chapter also explains the effects of a reset on the CPU and includes dis-
cussion of the automatic context save performed by the CPU prior to servic-
ing an interrupt.
Pipeline
This chapter describes the phases and operation of the instruction pipeline.
The chapter is primarily for readers interested in increasing the efficiency of
their programs by preventing pipeline delays.
Addressing Modes
This chapter explains the modes by which the assembly language instruc-
tions accept data and access register and memory locations. The chapter in-
cludes a description of how addressing-mode information is encoded in op-
codes.
Assembly Language Instructions
This chapter provides summaries of the instruction set and detailed descrip-
tions (including examples) for the instructions. The chapter includes an ex-
planation of how 32-bit accesses are aligned to even addresses.
Preface

Read This First

Read This First iii