Case 4-Chip Select Asserted Right Before The Rising Edge Of Aclk - Analog Devices ADSP-BF506F Hardware Reference Manual

Case 4—Chip Select Asserted Right Before the Rising
Edge of ACLK
When is asserted right before the rising edge of ACLK, the high phase
CS
of ACLK is extended, as shown in
SCLK
Ref ACLK1
CS
ACLK
Figure 22-13. ACLK Adjustment for the Case of
the Rising Edge of ACLK (CLKPOL =0)
This extension ensures that the time from the active edge of
ing edge of ACLK is constant at a period of 1 ACLK cycle. Notice that
this leads to duty cycle variation. It is important to ensure that systems
interfacing with the ACM can tolerate such duty cycle variation.
ADSP-BF50x Blackfin Processor Hardware Reference
ADC Control Module (ACM)
Figure 22-13.
1
Edges Suppressed
Duty Phase
Cycle Changed
Variation
2
Assertion Right Before
CS
to the fall-
CS
22-25