Table 5.6 Interrupt Source Selection And Clear Control - Renesas H8SX/1500 Series Hardware Manual

(1)
Selection of Interrupt Sources
The activation source for each DMAC channel is selected by DMRSR. The selected activation
source is input to the DMAC through the select circuit. When transfer by an on-chip module
interrupt is enabled (DTF1 = 1, DTF0 = 0, and DTE = 1 in DMDR) and the DTA bit in DMDR is
set to 1, the interrupt source selected for the DMAC activation source is controlled by the DMAC
and cannot be used as a CPU interrupt source.
Interrupt sources that are not controlled by the DMAC can be CPU interrupt sources.
When the same interrupt source is set as both the DMAC activation source and CPU interrupt
source, the DMAC must be given priority over the CPU. If the IPSETE bit in CPUPCR is set to 1,
the priority is determined according to the IPR setting. Therefore, the CPUP setting or the IPR
setting corresponding to the interrupt source must be set to lower than or equal to the DMAP
settings. If the CPU is given priority, the DMAC may not be activated and the data transfer may
be performed.
(2)
Operation Order
If the same interrupt is selected as both the DMAC activation source and CPU interrupt source, the
respective operations are performed independently.
Table 5.6 lists the selection of interrupt sources and interrupt source clear control by means of the
setting of the DTA bit in DMDR of the DMAC.
Table 5.6 Interrupt Source Selection and Clear Control
Setting
DMAC
DTA
0
1
[Legend]
√: The corresponding interrupt is used. The interrupt source is cleared.
(The interrupt source flag must be cleared in the CPU interrupt handling routine.)
O: The corresponding interrupt is used. The interrupt source is not cleared.
X: The corresponding interrupt is not available.
(3) Usage Note
The interrupt sources of the SCI, A/D converter, HCAN and SSU are cleared according to the
setting shown in table 5.6, when the DMAC reads/writes the prescribed register.
Interrupt Source Selection/Clear Control
DMAC
O
√
Section 5 Interrupt Controller
CPU
√
X
Rev. 3.00 Mar. 14, 2006 Page 119 of 804
REJ09B0104-0300