ST STM32L4+ Series Reference Manual page 1452

General-purpose timers (TIM15/TIM16/TIM17)
Bit 31 UIFCPY: UIF Copy
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
39.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17)
Address offset: 0x28
Reset value: 0x0000
15 14 13
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Bits 15:0 PSC[15:0]: Prescaler value
39.6.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17)
Address offset: 0x2C
Reset value: 0xFFFF
15 14 13
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Bits 15:0 ARR[15:0]: Auto-reload value
1452/2301
This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in
TIMx_CR1 is reset, bit 31 is reserved and read as 0.
12 11 10 9
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The counter clock frequency (CK_CNT) is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in "reset mode").
12 11 10 9
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ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 39.4.1: Time-base unit on page 1379
update and behavior.
The counter is blocked while the auto-reload value is null.
8 7 6
PSC[15:0]
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8 7 6
ARR[15:0]
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RM0432 Rev 6
5 4 3 2
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/ (PSC[15:0] + 1).
CK_PSC
5 4 3 2
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for more details about ARR
RM0432
1 0
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1 0
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