Sign In
Upload
Manuals
Brands
Texas Instruments Manuals
Controller
TMS320DM357
Texas Instruments TMS320DM357 Manuals
Manuals and User Guides for Texas Instruments TMS320DM357. We have
3
Texas Instruments TMS320DM357 manuals available for free PDF download: User Manual, Getting Started Manual
Texas Instruments TMS320DM357 User Manual (167 pages)
DMSoC Enhanced Direct Memory Access (EDMA3) Controller
Brand:
Texas Instruments
| Category:
Microcontrollers
| Size: 1 MB
Table of Contents
Table of Contents
3
Preface
13
1 Introduction
17
Overview
18
Features
18
Terminology Used in this Document
19
2 EDMA3 Architecture
21
Functional Overview
22
EDMA3 Controller Block Diagram
22
EDMA3 Channel Controller (EDMA3CC)
22
EDMA3 Channel Controller (EDMA3CC) Block Diagram
23
EDMA3 Transfer Controller (EDMA3TC)
24
EDMA3 Transfer Controller (EDMA3TC) Block Diagram
24
Types of EDMA3 Transfers
25
Definition of ACNT, BCNT, and CCNT
25
A-Synchronized Transfers
26
A-Synchronized Transfers (ACNT = N, BCNT = 4, CCNT = 3)
26
AB-Synchronized Transfers
27
AB-Synchronized Transfers (ACNT = N, BCNT = 4, CCNT = 3)
27
Parameter RAM (Param)
28
EDMA3 Parameter RAM Contents
28
Param Set
29
EDMA3 Channel Parameter Description
30
EDMA3 Channel Parameter Set Fields
31
Null Param Set
33
Dummy Param Set
33
Dummy Versus Null Transfer Comparison
33
Parameter Set Updates
33
Dummy and Null Transfer Request
33
Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy Param Set)
34
Linking Transfers
35
Linked Transfer
36
Link-To-Self Transfer
37
Initiating a DMA Transfer
38
DMA Channel
38
EDMA3 Channel Synchronization Events
38
QDMA Channels
41
Comparison between DMA and QDMA Channels
41
Completion of a DMA Transfer
42
Expected Number of Transfers for Non-Null Transfer
42
Normal Completion
43
Early Completion
43
Dummy or Null Completion
43
Event, Channel, and Param Mapping
43
DMA Channel to Param Mapping
44
QDMA Channel to Param Mapping
44
EDMA3 DMA Channel to Param Mapping
44
EDMA3 Channel Controller Regions
45
Region Overview
45
QDMA Channel to Param Mapping
45
Shadow Region Registers
46
Channel Controller Regions
47
Chaining EDMA3 Channels
47
EDMA3 Shadow Regions
47
Chain Event Triggers
48
EDMA3 Interrupts
49
Transfer Completion Interrupts
49
EDMA3 Transfer Completion Interrupts
49
EDMA3 Error Interrupts
49
Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping
50
Number of Interrupts
50
EDMA3 Interrupt Servicing
51
Interrupt Diagram
51
Interrupt Evaluation Operations
54
Error Interrupts
54
Event Queue(S)
55
Error Interrupt Operation
55
DMA/QDMA Channel to Event Queue Mapping
56
Queue RAM Debug Visibility
56
Queue Resource Tracking
56
Performance Considerations
56
EDMA3 Transfer Controller (EDMA3TC)
57
Architecture Details
57
Error Generation
58
Read/Write Command Optimization Rules
58
Debug Features
59
EDMA3TC Configuration
59
EDMA3 Transfer Controller Configurations
59
Event Dataflow
60
EDMA3 Prioritization
61
Channel Priority
61
Trigger Source Priority
62
Dequeue Priority
62
System (Transfer Controller) Priority
62
EDMA3 Operating Frequency (Clock Control)
62
Reset Considerations
62
Power Management
63
Emulation Considerations
63
3 EDMA3 Transfer Examples
65
Block Move Example
66
Block Move Example Param Configuration
67
Subframe Extraction Example
68
Subframe Extraction Example Param Configuration
69
Data Sorting Example
70
Data Sorting Example Param Configuration
71
Peripheral Servicing Example
72
Nonbursting Peripherals
72
Servicing Incoming ASP Data Example
72
Servicing Incoming ASP Data Example Param
73
Bursting Peripherals
74
Servicing Peripheral Burst Example
74
Servicing Peripheral Burst Example Param
75
Continuous Operation
76
Servicing Continuous ASP Data Example
76
Servicing Continuous ASP Data Example Param
77
Servicing Continuous ASP Data Example Reload Param
78
Ping-Pong Buffering
79
Ping-Pong Buffering for ASP Data Example
80
Ping-Pong Buffering for ASP Example Param
80
Ping-Pong Buffering for ASP Example Pong Param
81
Transfer Chaining Examples
82
Ping-Pong Buffering for ASP Example Ping Param
82
Intermediate Transfer Completion Chaining Example
83
Single Large Block Transfer Example
84
Smaller Packet Data Transfers Example
84
4 Registers
85
Register Memory Maps
86
Parameter RAM (Param) Entries
86
EDMA3 Channel Controller (EDMA3CC) Parameter RAM (Param) Entries
86
Channel Options Parameter (OPT)
87
Channel Options Parameters (OPT) Field Descriptions
87
Channel Source Address Parameter (SRC)
89
A Count/B Count Parameter (A_B_CNT)
89
Channel Source Address Parameter (SRC) Field Descriptions
89
A Count/B Count Parameter (A_B_CNT) Field Descriptions
89
Channel Destination Address Parameter (DST)
90
Source B Index/Destination B Index Parameter (SRC_DST_BIDX)
90
Channel Destination Address Parameter (DST) Field Descriptions
90
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions
90
Link Address/B Count Reload Parameter (LINK_BCNTRLD)
91
Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions
91
Source C Index/Destination C Index Parameter (SRC_DST_CIDX)
92
C Count Parameter (CCNT)
92
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions
92
C Count Parameter (CCNT) Field Descriptions
92
EDMA3 Channel Controller Control Registers
93
EDMACC Registers
93
Global Registers
97
Peripheral ID Register (PID)
97
EDMA3CC Configuration Register (CCCFG)
97
Peripheral ID Register (PID) Field Descriptions
97
EDMA3CC Configuration Register (CCCFG) Field Descriptions
98
QDMA Channel Map N Registers (Qchmapn)
99
QDMA Channel Map N Registers (Qchmapn) Field Descriptions
99
DMA Channel Queue Number Registers (Dmaqnumn)
100
DMA Channel Queue Number Registers (Dmaqnumn) Field Descriptions
100
Bits in Dmaqnumn
100
QDMA Channel Queue Number Register (QDMAQNUM)
101
QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions
101
Error Registers
102
Queue Priority Register (QUEPRI)
102
Queue Priority Register (QUEPRI) Field Descriptions
102
Event Missed Register (EMR)
103
Event Missed Register High (EMRH)
103
Event Missed Register (EMR) Field Descriptions
103
Event Missed Register High (EMRH) Field Descriptions
103
Event Missed Clear Register (EMCR)
104
Event Missed Clear Register High (EMCRH)
104
Event Missed Clear Register (EMCR) Field Descriptions
104
Event Missed Clear Register High (EMCRH) Field Descriptions
104
QDMA Event Missed Register (QEMR)
105
QDMA Event Missed Register (QEMR) Field Descriptions
105
QDMA Event Missed Clear Register (QEMCR)
106
QDMA Event Missed Clear Register (QEMCR) Field Descriptions
106
EDMA3CC Error Register (CCERR)
107
EDMA3CC Error Register (CCERR) Field Descriptions
107
EDMA3CC Error Clear Register (CCERRCLR)
108
EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions
108
Error Evaluation Register (EEVAL)
109
Error Evaluation Register (EEVAL) Field Descriptions
109
Region Access Enable Registers
110
DMA Region Access Enable Register for Region M (Draem)
110
DMA Region Access Enable High Register for Region M (Draehm)
110
DMA Region Access Enable Registers for Region M (Draem/Draehm) Field Descriptions
110
QDMA Region Access Enable for Region M (Qraem)
111
QDMA Region Access Enable for Region M (Qraem) Field Descriptions
111
Status/Debug Visibility Registers
112
Event Queue Entry Registers (Qxey)
112
Event Queue Entry Registers (Qxey) Field Descriptions
112
Queue N Status Register (Qstatn)
113
Queue N Status Register (Qstatn) Field Descriptions
113
Queue Watermark Threshold a Register (QWMTHRA)
114
Queue Watermark Threshold a Register (QWMTHRA) Field Descriptions
114
EDMA3CC Status Register (CCSTAT)
115
EDMA3CC Status Register (CCSTAT) Field Descriptions
115
DMA Channel Registers
116
Event Register (ER)
117
Event Register High (ERH)
117
Event Register (ER) Field Descriptions
117
Event Register High (ERH) Field Descriptions
117
Event Clear Register (ECR)
118
Event Clear Register High (ECRH)
118
Event Clear Register (ECR) Field Descriptions
118
Event Clear Register High (ECRH) Field Descriptions
118
Event Set Register (ESR)
119
Event Set Register (ESR) Field Descriptions
119
Event Set Register High (ESRH)
120
Event Set Register High (ESRH) Field Descriptions
120
Chained Event Register (CER)
121
Chained Event Register High (CERH)
121
Chained Event Register (CER) Field Descriptions
121
Chained Event Register High (CERH) Field Descriptions
121
Event Enable Register (EER)
122
Event Enable Register High (EERH)
122
Event Enable Register (EER) Field Descriptions
122
Event Enable Clear Register (EECR)
123
Event Enable Clear Register High (EECRH)
123
Event Enable Register High (EERH) Field Descriptions
123
Event Enable Clear Register (EECR) Field Descriptions
123
Event Enable Set Register (EESR)
124
Event Enable Set Register High (EESRH)
124
Event Enable Clear Register High (EECRH) Field Descriptions
124
Event Enable Set Register (EESR) Field Descriptions
124
Secondary Event Register (SER)
125
Event Enable Set Register High (EESRH) Field Descriptions
125
Secondary Event Register (SER) Field Descriptions
125
Secondary Event Register High (SERH)
126
Secondary Event Clear Register (SECR)
126
Secondary Event Register High (SERH) Field Descriptions
126
Secondary Event Clear Register (SECR) Field Descriptions
126
Secondary Event Clear Register High (SECRH)
127
Secondary Event Clear Register High (SECRH) Field Descriptions
127
Interrupt Registers
128
Interrupt Enable Register (IER)
128
Interrupt Enable Register High (IERH)
128
Interrupt Enable Register (IER) Field Descriptions
128
Interrupt Enable Register High (IERH) Field Descriptions
128
Interrupt Enable Clear Register (IECR)
129
Interrupt Enable Clear Register High (IECRH)
129
Interrupt Enable Clear Register (IECR) Field Descriptions
129
Interrupt Enable Clear Register High (IECRH) Field Descriptions
129
Interrupt Enable Set Register (IESR)
130
Interrupt Enable Set Register High (IESRH)
130
Interrupt Enable Set Register (IESR) Field Descriptions
130
Interrupt Enable Set Register High (IESRH) Field Descriptions
130
Interrupt Pending Register (IPR)
131
Interrupt Pending Register High (IPRH)
131
Interrupt Pending Register (IPR) Field Descriptions
131
Interrupt Pending Register High (IPRH) Field Descriptions
131
Interrupt Clear Register (ICR)
132
Interrupt Clear Register High (ICRH)
132
Interrupt Clear Register (ICR) Field Descriptions
132
Interrupt Clear Register High (ICRH) Field Descriptions
132
Interrupt Evaluate Register (IEVAL)
133
Interrupt Evaluate Register (IEVAL) Field Descriptions
133
QDMA Event Register (QER)
134
QDMA Event Register (QER) Field Descriptions
134
QDMA Event Enable Register (QEER)
135
QDMA Event Enable Register (QEER) Field Descriptions
135
QDMA Event Enable Clear Register (QEECR)
136
QDMA Event Enable Clear Register (QEECR) Field Descriptions
136
QDMA Event Enable Set Register (QEESR)
137
QDMA Event Enable Set Register (QEESR) Field Descriptions
137
QDMA Secondary Event Register (QSER)
138
QDMA Secondary Event Register (QSER) Field Descriptions
138
QDMA Secondary Event Clear Register (QSECR)
139
QDMA Secondary Event Clear Register (QSECR) Field Descriptions
139
EDMA3 Transfer Controller Registers
140
Peripheral ID Register (PID)
141
EDMA3TC Configuration Register (TCCFG)
142
EDMA3TC Configuration Register (TCCFG) Field Descriptions
142
EDMA3TC Channel Status Register (TCSTAT)
143
EDMA3TC Channel Status Register (TCSTAT) Field Descriptions
143
Error Status Register (ERRSTAT)
144
Error Status Register (ERRSTAT) Field Descriptions
144
Error Enable Register (ERREN)
145
Error Enable Register (ERREN) Field Descriptions
145
Error Clear Register (ERRCLR)
146
Error Clear Register (ERRCLR) Field Descriptions
146
Error Details Register (ERRDET)
147
Error Details Register (ERRDET) Field Descriptions
147
Error Interrupt Command Register (ERRCMD)
148
Error Interrupt Command Register (ERRCMD) Field Descriptions
148
Read Rate Register (RDRATE)
149
Read Rate Register (RDRATE) Field Descriptions
149
Source Active Options Register (SAOPT)
150
Source Active Options Register (SAOPT) Field Descriptions
150
Source Active Source Address Register (SASRC)
151
Source Active Count Register (SACNT)
151
Source Active Source Address Register (SASRC) Field Descriptions
151
Source Active Count Register (SACNT) Field Descriptions
151
Source Active Destination Address Register (SADST)
152
Source Active Source B-Dimension Index Register (SABIDX)
152
Source Active Destination Address Register (SADST) Field Descriptions
152
Source Active Source B-Dimension Index Register (SABIDX) Field Descriptions
152
Source Active Memory Protection Proxy Register (SAMPPRXY)
153
Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions
153
Source Active Count Reload Register (SACNTRLD)
154
Source Active Source Address B-Reference Register (SASRCBREF)
154
Source Active Count Reload Register (SACNTRLD) Field Descriptions
154
Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions
154
Source Active Destination Address B-Reference Register (SADSTBREF)
155
Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions
155
Destination FIFO Options Register (Dfoptn)
156
Destination FIFO Options Register (Dfoptn) Field Descriptions
156
Destination FIFO Source Address Register (Dfsrcn)
157
Destination FIFO Source Address Register (Dfsrcn) Field Descriptions
157
Destination FIFO Count Register (Dfcntn)
158
Destination FIFO Count Register (Dfcntn) Field Descriptions
158
Destination FIFO Destination Address Register (Dfdstn)
159
Destination FIFO B-Index Register (Dfbidxn)
159
Destination FIFO Destination Address Register (Dfdstn) Field Descriptions
159
Destination FIFO B-Index Register (Dfbidxn) Field Descriptions
159
Destination FIFO Memory Protection Proxy Register (Dfmpprxyn)
160
Destination FIFO Memory Protection Proxy Register (Dfmpprxyn) Field Descriptions
160
Destination FIFO Count Reload Register (Dfcntrldn)
161
Destination FIFO Source Address B-Reference Register (Dfsrcbrefn)
161
Destination FIFO Count Reload Register (Dfcntrldn) Field Descriptions
161
Destination FIFO Source Address B-Reference Register (Dfsrcbrefn) Field Descriptions
161
Destination FIFO Destination Address B-Reference Register (Dfdstbrefn)
162
Destination FIFO Destination Address B-Reference Register (Dfdstbrefn) Field Descriptions
162
SPRUG34 - November 2008
163
Debug List
163
Advertisement
Texas Instruments TMS320DM357 User Manual (144 pages)
DMSoC Universal Serial Bus (USB) Controller
Brand:
Texas Instruments
| Category:
Controller
| Size: 1 MB
Table of Contents
Table of Contents
3
Preface
11
Read this First
11
SPRUGH3 - November 2008
11
Introduction
14
Purpose of the Peripheral
14
Features
14
Features Not Supported
14
Universal Serial Bus (USB) Controller
14
Functional Block Diagram
15
Supported Use Case Examples
16
Industry Standard(S) Compliance Statement
22
Peripheral Architecture
23
Clock Control
23
Signal Descriptions
23
Indexed and Non-Indexed Registers
23
USB Pins
23
USB PHY Initialization
24
Dynamic FIFO Sizing
24
USB Controller Host and Peripheral Modes Operation
24
Interrupt Service Routine Flow Chart
25
USB Controller Peripheral Mode Operation
26
CPU Actions at Transfer Phases
29
Sequence of Transfer
30
Service Endpoint 0 Flow Chart
32
IDLE Mode Flow Chart
33
TX Mode Flow Chart
34
RX Mode Flow Chart
35
PERI_TXCSR Register Bit Configuration for Bulk in Transactions
37
PERI_RXCSR Register Bit Configuration for Bulk out Transactions
39
PERI_TXCSR Register Bit Configuration for Isochronous in Transactions
41
PERI_RXCSR Register Bit Configuration for Isochronous out Transactions
43
USB Controller Host Mode Operation
44
Setup Phase of a Control Transaction Flow Chart
45
IN Data Phase Flow Chart
47
OUT Data Phase Flow Chart
48
Completion of SETUP or out Data Phase Flow Chart
49
Completion of in Data Phase Flow Chart
51
DMA Operation
57
Transmit Buffer Descriptor Word 2
58
Transmit Buffer Descriptor Word
58
Transmit Buffer Descriptor Word 3
58
Tx Queue Flow Chart
60
Receive Buffer Descriptor Word 2
63
Receive Buffer Descriptor Word
63
Receive Buffer Descriptor Word
64
Rx Queue Flow Chart
65
Interrupt Handling
68
Interrupts Generated by the USB Controller
68
USB Interrupt Conditions
68
Test Modes
70
Reset Considerations
74
Interrupt Support
74
EDMA Event Support
74
Power Management
74
Registers
75
Universal Serial Bus (USB) Registers
75
Control Register (CTRLR)
82
Control Register (CTRLR) Field Descriptions
82
Status Register (STATR)
83
RNDIS Register (RNDISR)
83
Status Register (STATR) Field Descriptions
83
RNDIS Register (RNDISR) Field Descriptions
83
Auto Request Register (AUTOREQ)
84
Auto Request Register (AUTOREQ) Field Descriptions
84
USB Interrupt Source Register (INTSRCR)
85
USB Interrupt Source Register (INTSRCR) Field Descriptions
85
USB Interrupt Source Set Register (INTSETR)
86
USB Interrupt Source Set Register (INTSETR) Field Descriptions
86
USB Interrupt Source Clear Register (INTCLRR)
87
USB Interrupt Source Clear Register (INTCLRR) Field Descriptions
87
USB Interrupt Mask Register (INTMSKR)
88
USB Interrupt Mask Register (INTMSKR) Field Descriptions
88
USB Interrupt Mask Set Register (INTMSKSETR)
89
USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions
89
USB Interrupt Mask Clear Register (INTMSKCLRR)
90
USB Interrupt Mask Clear Register (INTMSKCLRR) Field Descriptions
90
USB Interrupt Source Masked Register (INTMASKEDR)
91
USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions
91
USB End of Interrupt Register (EOIR)
92
USB Interrupt Vector Register (INTVECTR)
92
USB End of Interrupt Register (EOIR) Field Descriptions
92
USB Interrupt Vector Register (INTVECTR) Field Descriptions
92
Transmit CPPI Control Register (TCPPICR)
93
Transmit CPPI Teardown Register (TCPPITDR)
93
Transmit CPPI Control Register (TCPPICR) Field Descriptions
93
Transmit CPPI Teardown Register (TCPPITDR) Field Descriptions
93
CPPI DMA End of Interrupt Register (CPPIEOIR)
94
CPPI DMA End of Interrupt Register (CPPIEOIR) Field Descriptions
94
Transmit CPPI Masked Status Register (TCPPIMSKSR)
95
Transmit CPPI Raw Status Register (TCPPIRAWSR)
95
Transmit CPPI Masked Status Register (TCPPIMSKSR) Field Descriptions
95
Transmit CPPI Raw Status Register (TCPPIRAWSR) Field Descriptions
95
Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR)
96
Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR)
96
Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) Field Descriptions
96
Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) Field Descriptions
96
Receive CPPI Control Register (RCPPICR)
97
Receive CPPI Masked Status Register (RCPPIMSKSR)
97
Receive CPPI Control Register (RCPPICR) Field Descriptions
97
Receive CPPI Masked Status Register (RCPPIMSKSR) Field Descriptions
97
Receive CPPI Raw Status Register (RCPPIRAWSR)
98
Receive CPPI Interrupt Enable Set Register (RCPPIENSETR)
98
Receive CPPI Raw Status Register (RCPPIRAWSR) Field Descriptions
98
Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) Field Descriptions
98
Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR)
99
Receive Buffer Count 0 Register (RBUFCNT0)
99
Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) Field Descriptions
99
Receive Buffer Count 0 Register (RBUFCNT0) Field Descriptions
99
Receive Buffer Count 1 Register (RBUFCNT1)
100
Receive Buffer Count 2 Register (RBUFCNT2)
100
Receive Buffer Count 1 Register (RBUFCNT1) Field Descriptions
100
Receive Buffer Count 2 Register (RBUFCNT2) Field Descriptions
100
Receive Buffer Count 3 Register (RBUFCNT3)
101
Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0)
101
Receive Buffer Count 3 Register (RBUFCNT3) Field Descriptions
101
Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) Field Descriptions
101
Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1)
102
Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2)
102
Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) Field Descriptions
102
Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) Field Descriptions
102
Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3)
103
Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4)
103
Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) Field Descriptions
103
Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) Field Descriptions
103
Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5)
104
Transmit CPPI Completion Pointer (TCPPICOMPPTR)
104
Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) Field Descriptions
104
Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0)
105
Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1)
105
Transmit CPPI Completion Pointer (TCPPICOMPPTR) Field Descriptions
105
Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) Field Descriptions
105
Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1)
106
Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) Field Descriptions
106
Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2)
107
Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3)
107
Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) Field Descriptions
107
Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) Field Descriptions
107
Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4)
109
Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5)
109
Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) Field Descriptions
109
Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) Field Descriptions
109
Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6)
110
Receive CPPI Completion Pointer (RCPPICOMPPTR)
110
Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) Field Descriptions
110
Receive CPPI Completion Pointer (RCPPICOMPPTR) Field Descriptions
110
Function Address Register (FADDR)
111
Power Management Register (POWER)
111
Function Address Register (FADDR) Field Descriptions
111
Power Management Register (POWER) Field Descriptions
111
Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX)
112
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX)
112
Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX)
112
Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) Field Descriptions
112
Interrupt Enable Register for INTRRX (INTRRXE)
113
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX)
113
Interrupt Enable Register for INTRTX (INTRTXE)
113
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Field Descriptions
113
Interrupt Enable Register for INTRTX (INTRTXE) Field Descriptions
113
Interrupt Enable Register for INTRRX (INTRRXE)
114
Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions
114
Interrupt Register for Common USB Interrupts (INTRUSB)
115
Interrupt Register for Common USB Interrupts (INTRUSB) Field Descriptions
115
Interrupt Enable Register for INTRUSB (INTRUSBE)
116
Interrupt Enable Register for INTRUSB (INTRUSBE) Field Descriptions
116
Frame Number Register (FRAME)
117
Index Register for Selecting the Endpoint Status and Control Registers (INDEX)
117
Frame Number Register (FRAME) Field Descriptions
117
Index Register for Selecting the Endpoint Status and Control Registers (INDEX) Field Descriptions
117
Register to Enable the USB 2.0 Test Modes (TESTMODE)
118
Register to Enable the USB 2.0 Test Modes (TESTMODE) Field Descriptions
118
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)
119
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) Field Descriptions
119
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0)
120
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) Field Descriptions
121
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)
122
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions
123
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP)
124
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Field Descriptions
124
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR)
125
Control Status Register for Host Receive Endpoint (HOST_RXCSR) Field Descriptions
126
Count 0 Register (COUNT0)
128
Receive Count Register (RXCOUNT)
128
SPRUGH3 - November 2008 Submit Documentation Feedback
128
Count 0 Register (COUNT0) Field Descriptions
128
Receive Count Register (RXCOUNT) Field Descriptions
128
Type Register (Host Mode Only) (HOST_TYPE0) Field Descriptions
129
Type Register (Host Mode Only) (HOST_TYPE0)
129
Transmit Interval Register (Host Mode Only) (HOST_TXINTERVAL)
130
Naklimit0 Register (Host Mode Only) (HOST_NAKLIMIT0) Field Descriptions
130
Transmit Interval Register (Host Mode Only) (HOST_TXINTERVAL) Field Descriptions
130
Receive Interval Register (Host Mode Only) (HOST_RXINTERVAL)
131
Receive Type Register (Host Mode Only) (HOST_RXTYPE) Field Descriptions
131
Configuration Data Register (CONFIGDATA)
132
Receive Interval Register (Host Mode Only) (HOST_RXINTERVAL) Field Descriptions
132
Configuration Data Register (CONFIGDATA) Field Descriptions
132
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0)
134
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) Field Descriptions
134
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1)
135
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2)
135
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) Field Descriptions
135
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) Field Descriptions
135
Transmit and Receive FIFO Register for Endpoint 3 (FIFO3)
136
Transmit and Receive FIFO Register for Endpoint 4 (FIFO4)
136
Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions
136
Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions
136
OTG Device Control Register (DEVCTL)
137
OTG Device Control Register (DEVCTL) Field Descriptions
137
Transmit Endpoint FIFO Size (TXFIFOSZ)
138
Receive Endpoint FIFO Size (RXFIFOSZ)
138
Transmit Endpoint FIFO Size (TXFIFOSZ) Field Descriptions
138
Receive Endpoint FIFO Size (RXFIFOSZ) Field Descriptions
138
Transmit Endpoint FIFO Address (TXFIFOADDR)
139
Receive Endpoint FIFO Address (RXFIFOADDR)
139
Transmit Endpoint FIFO Address (TXFIFOADDR) Field Descriptions
139
Receive Endpoint FIFO Address (RXFIFOADDR) Field Descriptions
139
Transmit Function Address (TXFUNCADDR)
140
Transmit Hub Address (TXHUBADDR)
140
Transmit Hub Port (TXHUBPORT)
140
Transmit Function Address (TXFUNCADDR) Field Descriptions
140
Transmit Hub Address (TXHUBADDR) Field Descriptions
140
Transmit Hub Port (TXHUBPORT) Field Descriptions
140
Receive Function Address (RXFUNCADDR)
141
Receive Hub Address (RXHUBADDR)
141
Receive Hub Port (RXHUBPORT)
141
Receive Function Address (RXFUNCADDR) Field Descriptions
141
Receive Hub Address (RXHUBADDR) Field Descriptions
141
Receive Hub Port (RXHUBPORT) Field Descriptions
141
Appendix A Revision History
143
Document Revision History
143
Important Notice
144
Texas Instruments TMS320DM357 Getting Started Manual (68 pages)
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 0 MB
Table of Contents
About this Guide
5
Notational Conventions
5
Table of Contents
7
DVEVM Overview
9
This Chapter Introduces the DVEVM (Digital Video Evaluation Module)
9
What's in this Kit
10
What's on the Board
11
What's Next
12
EVM Hardware Setup
13
Setting up the Hardware
14
Connecting to a Console Window
18
Running the Demonstration Software
19
Chapter 3
20
Default Boot Configuration
20
Starting the Standalone Demos
20
Running the Standalone Demos
23
Shutting down the Demos
24
About the Encode + Decode Demo
25
About the Encode Demo
25
About the Decode Demo
27
Running the Demos from the Command Line
28
Running the Network Demo
29
DVEVM Software Setup
31
Chapter 4
32
Software Overview
32
Command Prompts in this Guide
33
Software Components
34
Preparing to Install
35
Installing the Software
36
Installing the Target Linux Software
36
Installing the DVSDK Software
37
Installing the A/V Demo Files
38
Exporting a Shared File System for Target Access
38
Testing the Shared File System
40
Notes on Using Evaluation/Production Codecs
41
Setting up the Build/Development Environment
42
Writing a Simple Program and Running It on the EVM
42
Building a New Linux Kernel
43
Rebuilding the DVEVM Software for the Target
44
Building with Dsplink
45
Booting the New Linux Kernel
46
Using the Digital Video Test Bench (DVTB)
47
Additional Procedures
49
A.1 Changing the Video Input/Output Methods
49
This Appendix Describes Optional Procedures You May Use Depending on Your Setup and Specific
50
Appendix A
50
Changing the Video Input/Output Methods
50
Putting Demo Applications in the Third-Party Menu
51
Setting up a TFTP Server
53
Alternate Boot Methods
54
Updating/Restoring the Bootloaders
57
Restoring the NAND Flash
60
Advertisement
Advertisement
Related Products
Texas Instruments TMS320DM644x
Texas Instruments TMS320DM647
Texas Instruments TMS320DM646 Series
Texas Instruments TMS320C6455
Texas Instruments TMS320C6454
Texas Instruments TMS320C674X
Texas Instruments TMS320C6452 DSP
Texas Instruments TMS320C6742
Texas Instruments TMS320C6748
texas instruments TMS320x281 series
Texas Instruments Categories
Motherboard
Control Unit
Microcontrollers
Computer Hardware
Calculator
More Texas Instruments Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL