Port A Data Register (Padr) - Renesas HD6417641 Hardware Manual

Section 23 I/O Ports
23.1.2

Port A Data Register (PADR)

PADR is a 15-bit readable/writable register with one reserved bit that stores data for pins PTA14
to PTA0. PADR is initialized to H'0000 by a power-on reset, but it retains its previous value by a
manual reset, in standby mode or in sleep mode.
Bit Bit Name

15
14 PA14DT
13 PA13DT
12 PA12DT
11 PA11DT
10 PA10DT
9 PA9DT
8 PA8DT
7 PA7DT
6 PA6DT
5 PA5DT
4 PA4DT
3 PA3DT
2 PA2DT
1 PA1DT
0 PA0DT
Rev. 4.00 Sep. 14, 2005 Page 844 of 982
REJ09B0023-0400
Initial
Value R/W Description
0 R Reserved
This bit is always read as 0. The write value should
always be 0.
0 R/W Bits PA14DT to PA0DT correspond to pins PTA14 to
PTA0. When the pin function is general output port, the
0 R/W
value of the corresponding PADR bit in PADR is
0 R/W
returned directly by reading the port. When the function
is general input port, the corresponding pin level is read
0 R/W
by reading the port. Table 23.1 shows the function of
0 R/W
PADR.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W