Port A Data Register (Padr); Port A Register (Porta) - Renesas H8S Series Hardware Manual

Section 9 I/O Ports
9.4.2

Port A Data Register (PADR)

PADR is an 8-bit readable/writable register that stores output data for port A pins.
Bit Bit Name
7 —
6 —
5 —
4 —
3 PA3DR
2 PA2DR
1 PA1DR
0 PA0DR
9.4.3

Port A Register (PORTA)

PORTA is an 8-bit read-only register that shows port A pin states.
PORTA cannot be modified.
Bit Bit Name
7 —
6 —
5 —
4 —
3 PA3
2 PA2
1 PA1
0 PA0
Note: * Determined by the states of pins PA3 to PA0.
Rev. 6.00 Mar 15, 2006 page 138 of 570
REJ09B0211-0600
Initial Value R/W
Undefined —
Undefined —
Undefined —
Undefined —
0 R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W
Undefined —
Undefined —
Undefined —
Undefined —
Undefined *
R
Undefined *
R
Undefined *
R
Undefined *
R
Description
Reserved
These bits are read as an undefined value.
Output data for a pin is stored when the pin is
specified as a general purpose I/O port.
Description
Reserved
These bits are read as an undefined value.
If a port A read is performed while PADDR bits are
set to 1, the PADR values are read. If a port A read
is performed while PADDR bits are cleared to 0, the
pin states are read.