Clock; Figure 14.4 Relationship Between Output Clock And Transfer Data Phase (Asynchronous Mode) - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input at

the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in

SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the

clock frequency should be 16 times the bit rate used.

When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The

frequency of the clock output in this case is equal to the bit rate, and the phase is such that the

rising edge of the clock is in the middle of the transmit data, as shown in figure 14.4.

Figure 14.4 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode)

Section 14 Serial Communication Interface (SCI)

Rev. 6.00 Mar 15, 2006 page 341 of 570

REJ09B0211-0600