Conflict Between Input Capture And Tdpicr Read; Conflict Between Edge Detection In Cycle Measurement Mode And Writing To The Upper Limit Or Lower Limit Register - Renesas H8S/2100 Series Hardware Manual

Section 12 16-Bit Duty Period Measurement Timer (TDP)
12.6.3

Conflict between Input Capture and TDPICR Read

When the corresponding input capture signal is detected during reading of TDPICR in timer mode,
the input capture signal is delayed by one cycle of the system clock (φ). Figure 12.15 shows the
timing of this conflict.
φ
TDPCYI
TDPICR
read signal
Input capture
signal
TDPCNT
TDPICR
ICPF
Figure 12.15 Conflict between Input Capture and TDPICR Read
12.6.4 Conflict between Edge Detection in Cycle Measurement Mode and Writing to the
Upper Limit or Lower Limit Register
If the edge of TDPCYI is detected in the second half of a cycle of writing to any of the upper
limit/lower limit registers (TDPPDMX, TDPPDMN, TDPWDMX, and TDPWDMN) in cycle
measurement mode, the detected edge signal is delayed by one cycle of the system clock (φ).
Figure 12.16 shows the timing of this conflict.
φ
TDPCYI
Internal write
signal
Input capture
signal
TDPCNT
TDPICR
TPDMXOVF
Figure 12.16 Conflict between Edge Detection and Register Write
Rev. 1.00 Apr. 28, 2008 Page 352 of 994
REJ09B0452-0100
N - 1 N Capture occurs
M
Capture occurs
N
M
(Cycle Measurement Mode)
N + 1
N
H'0000
N
TDPICR > TDPPDMX (Cycle upper limit exceeded)
N + 2