Handling Of Each Pin In Test Mode - Renesas NU85E Preliminary User's Manual

9.4 Handling of Each Pin in Test Mode

(1) Pins other than those for test mode
(a) Input pins
Input a low level to the VAREQ pin. Special handling is not required for pins other than the VAREQ pin
(handle as in normal mode).
(b) Output pins
Special handling is not required (handle as in normal mode).
(2) Test mode pins (except TBI39 to TBI0, TBO34 to TBO0, BUNRI, TEST, and BUNRIOUT)
Handle the pins for test mode as indicated below.
Pin Name I/O
When MEMC Is Connected
PHTDOn Input Connect to the PHTDOn pin of
the NT85E500.
PHTDINn Output Connect to the PHTDINn pin of
the NT85E500.
VPRESZ Output Connect to the VPRESZ pin of
the NT85E500, NT85E502.
VPTCLK Output Connect to the VPTCLK pin of
the NT85E500, NT85E502.
−
TESEN Output
PHTEST Output Connect to the PHTEST pin of
the NT85E500.
TMODEn, Output Leave open.
TBREDZ
Remark n = 1, 0
(3) Precautions when NB85E901 is connected
When the NB85E901 (RCU) is connected to the NU85E, the following pins are used in the unit test mode. All of
these pins should be attached off chip as external pins.
• TBI39 to TBI0
Note 1
• TBO34 to TBO0
Note 1
• TEST Note 1
• BUNRI
• DCK
Note 2
Notes 1. Can be used as an alternate function pin with a pin used in normal mode.
2. Pins of the NB85E901 (For details, refer to CHAPTER 10 NB85E901.)
CHAPTER 9 TEST FUNCTION
Connection Method
When Cache Is Connected
−
−
Connect to the VPRESZ pin.
Connect to the VPTCLK pin.
−
−
• DRSTZ
Note 2
• DMS
Note 2
• DDI Note 2
• DDO Note 2
• DBINT
Notes 1, 2
Preliminary User's Manual A14874EJ3V0UM
When Neither MEMC nor Cache
Is Connected
Input low level.
Leave open.
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