Host Interface Shutdown Function (Lpcpd); Table 15.6 Scope Of Initialization In Each Host Interface Mode - Renesas H8S/2111B Hardware Manual

The scope of the initialization in each mode is shown in table 15.6.

Table 15.6 Scope of Initialization in Each Host Interface Mode

Items Initialized
LPC transfer cycle sequencer (internal state), LPCBSY and
ABRT flags
SERIRQ transfer cycle sequencer (internal state), CLKREQ and
IRQBSY flags
Host interface flags
(IBF1, IBF2, IBF3A, IBF3B, MWMF, C/D1, C/D2, C/D3, OBF1,
OBF2, OBF3A, OBF3B, SWMF, DBU), GA20 (internal state)
Host interrupt enable bits
(IRQ1E1, IRQ12E1, SMIE2, IRQ6E2,
IRQ9E2 to IRQ11E2, SMIE3B, SMIE3A, IRQ6E3, IRQ9E3 to
IRQ11E3), Q/C flag, SELREQ bit
LRST flag
SDWN flag
LRSTB bit
SDWNB bit
SDWNE bit
Host interface operation control bits
(LPC3E to LPC1E, FGA20E, LADR3,
IBFIE1 to IBFIE3, PMEE, PMEB, LSMIE, LSMIB, LSCIE, LSCIB,
TWRE, SELSTR3, SELIRQ1, SELSMI, SELIRQ6, SELIRQ9,
SELIRQ10, SELIRQ11, SELIRQ12)
LRESET signal
LPCPD signal
LAD3 to LAD0, LFRAME, LCLK, SERIRQ,
CLKRUN signals
PME, LSMI, LSCI, GA20 signals (when function is selected)
PME, LSMI, LSCI, GA20 signals (when function is not selected)
Note: System reset: Reset by STBY input, RES input, or WDT overflow
LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR)
LPC shutdown: Reset by LPC hardware shutdown (HS) or LPC software shutdown (SS)
System
Reset LPC Reset
Initialized Initialized
Initialized Initialized
Initialized Initialized
Initialized Initialized
Initialized Can be
(0) set/cleared
Initialized Initialized
(0) (0)
Initialized HR: 0
(0) SR: 1
Initialized Initialized
(0) (0)
Initialized Initialized
(0) (0)
Initialized Retained
Input (port Input
function
Input
Input
Output
Port function
Rev. 1.00, 05/04, page 403 of 544
LPC
Shutdown
Initialized
Initialized
Retained
Retained
Can be
set/cleared
Can be
set/cleared
0 (can be set)
HS: 0
SS: 1
HS: 1
SS: 0 or 1
Retained
Input
Input
Hi-Z
Hi-Z
Port function