C Bus Interface Mode - Renesas R8C Series User Manual

R8C/1A Group, R8C/1B Group
2
16.3.3 I

C bus Interface Mode

2
16.3.3.1 I C bus Format
Setting the FS bit in the SAR register to 0 communicates in I
Figure 16.32 shows the I
8 bits.
2
(1) I C bus format
2
(a) I C bus format (FS = 0)
S SLA
1
7
2
(b) I C bus format (when start condition is retransmitted, FS = 0)
S SLA
1
7
2
(2) I C bus timing
SDA
SCL
1 to 7
S
Explanation of symbols
S : Start condition
The master device changes the SDA signal from "H" to "L" while the SCL signal is held "H".
SLA : Slave address
R/W : Indicates the direction of data transmit/receive
Data is transmitted from the slave device to the master device when R/W value is 1 and from the master device to the slave device when
R/W value is 0.
A : Acknowledge
The receive device sets the SDA signal to "L".
DATA : Transmit / receive data
P : Stop condition
The master device changes the SDA signal from "L" to "H" while the SCL signal is held "H".
2
Figure 16.32 I C bus Format and Bus Timing
Rev.1.30 Dec 08, 2006
REJ09B0252-0130
2
C bus Format and Bus Timing. The 1st frame following the start condition consists of
R/W A DATA
1 1
n
1
R/W A
DATA
1 1
n1
1 m1
8 9 1 to 7
SLA R/W A DATA
Page 211 of 315
16. Clock Synchronous Serial Interface
2
C bus format.
A A/A P
1 1 1
Transfer bit count (n = 1 to 8)
m
Transfer frame count (m = from 1)
A/A S SLA
1
1
7
1
8 9 1 to 7 8
A DATA
R/W A
DATA
1 1
n2
m2
Upper: Transfer bit count (n1, n2 = 1 to 8)
Lower: Transfer frame count (m1, m2 = 1 or more)
9
A P
A/A P
1 1