Reset Operation; Fig. 2.15.1 Timing Diagram At Reset - Renesas 7200 Series User Manual

2.15 Reset
To reset the microcomputer, applied LOW level to pin RESET for 2 µ s or more. Reset is released when
HIGH level is applied to pin RESET, and the program starts from the address indicated with the reset vector
table.

2.15.1 Reset operation

If pin RESET is returned to an HIGH level after being held LOW for 2 µ s or more when the power source
voltage is within the recommended range (4.5 V to 5.5 V), timers 3 and 4 are connected by hardware with
internally reset state (internal timing signal φ is not supplied).
At this time, "FF " is set to timer 3, and "07
16
source; timer 4 counts down the timer 3 overflow signal (even when the device is in internally reset state,
f(X ) is continuously supplied to timer 3).
IN
The internal reset is released by timer 4 overflow, and the program is started from an address determined
with the contents of address FFFF
address). Figure 2.15.1 shows this sequence.
X
IN
φ
RESET
Internal
reset
SYNC
Address
Data
32,768 counts of f(X
timers 3 and 4
) and f( φ ) are in the relation : f(X
Notes 1: f(X
IN
2: A question mark (?) indicates an undefined state that depends on the previous state.
3: Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, "FF
is set in timer 3 and "07
state is released by the timer 4 overflow signal.

Fig. 2.15.1 Timing diagram at reset

FUNCTIONAL DESCRIPTION
" is set to timer 4. Timer 3 counts down f(X
16
(as high-order address) and contents of address FFFE
16
? ? 01,S
? ? PC
) by
IN
) = 2•f( φ ).
IN
" is set to timer 4. Timer 3 counts down with f(X
16
7220 Group User's Manual
01,S–1 01,S–2 FFFE
16
PC PS AD
H L
2.15 Reset
)/16 as its count
IN
(as low-order
16
AD ,
H
FFFF
16
AD
L
AD
L H
"
16
)/16, and reset
IN
2-95