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(2) Separate Bus, With Wait, Accessing External Memory Area
Table 5.3 and Figure 5.2 show the bus timing in memory expansion and microprocessor modes (with
wait, accessing external area).
Table 5.3 Memory expansion and microprocessor modes (with wait, accessing external area)
Symbol
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
th(RD-AD)
Address output hold time (RD standard)
th(WR-AD)
Address output hold time (WR standard)
td(BCLK-CS)
Chip-select output delay time
th(BCLK-CS)
Chip-select output hold time (BCLK standard)
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (BCLK standard)
th(BCLK-DB)
Data output hold time (BCLK standard)
td(DB-WR)
Data output delay time (WR standard)
th(WR-DB)
Data output hold time (WR standard)
*1 Calculated by the following formula according to the frequency of BCLK.
9
10
td(DB-WR)=
f(BCLK)
Item
-50 [ns]
( 63 / 84 )
Actual MCU
This product
[ns]
[ns]
Min.
Max.
Min.
50
See left
4
See left
0
See left
0
-4
50
See left
4
See left
40
See left
-4
See left
40
See left
0
See left
40
See left
0
See left
50
See left
4
See left
(*1)
See left
0
See left
Max.
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