Motorola MPC860 PowerQUICC User Manual page 1101

TDI, 3-15, 13-20
TDO, 3-15, 13-20
TEA, 3-4, 13-6, 14-5, 14-33, 20-22
termination signals protocol, 14-33
TEXP, 3-8, 13-11
TMS, 3-15, 13-20
TRST, 3-15, 13-20
TS, 3-4, 13-5, 14-4, 14-29
TSIZn, 3-3, 13-5, 14-4, 14-30
UPWAITx, 3-8, 13-10
VF, 37-3
VFLS, 37-3
WAIT_x, 3-9, 13-11
WEn, 3-7, 13-9
XFC, 3-8, 13-11, 15-8
XTAL, 3-8, 13-11
signals
external
illustration,, 3-2
system bus,, 3-3
SIMASK (SIU interrupt mask) register, 11-17
Single-beat read flow bus operation, 14-7
Single-beat transfer bus operation, 14-7
Single-beat write flow bus operation, 14-9
SIU interrupt vector (SIVEC) register, 11-19
SIU, see System interface unit
SIUMCR (SIU module configuration register), 11-5
Slow go mode, 18-6
SMCE (SMC event) register, 30-18
GCI mode, 30-36
transparent mode, 30-29
SMCM (SMC mask) register, 30-18
GCI mode, 30-36
transparent mode, 30-29
SMCMRs (SMC mode registers), 30-3
SMSYN signal, 30-22
Snooping
external bus activity, 8-28
Software monitor debug support
freeze indication, 37-35
overview, 37-35
Software watchdog reset, 12-3
Software watchdog timer (SWT), 11-21
SPCOM (SPI command) register, 31-10
SPIE (SPI event) register, 31-10
SPIM (SPI mask) register, 31-10
SPLL (system phase-locked loop) signals, 15-8
SPMODE (SPI mode) register, 31-7
SPRs
accessing off-core SPRs, 10-8
SRAM interface, 16-18
SRESET
external, 12-2, 12-4
internal, 12-4
reset configuration, 12-11
MOTOROLA
INDEX
reset sequence, 12-5
SRESET (soft reset) signal, 3-8, 13-11
Status mask (SMASK) register, 33-4
Storage reservation, 14-34
String instruction timing, 10-8
String instructions, D-23
STS (special transfer start) signal, 14-4
SWSR (software service register), 11-22
SWT, see Software watchdog timer
Synchronization
description, 6-6
memory synchronization instructions, D-23
clock (SYNCCLK) signal, 15-14
SYPCR (system protection control register), 11-9
System clock, 15-9
System configuration
interrupt structure, 11-12
overview, 11-2
System development functions, 37-1
System interface unit
programming the interrupt controller, 11-16
System interface unit (SIU)
bus monitor, 11-20
features summary, 11-1
overview, 11-1
programming the SIU, 11-4
System linkage instructions, D-25
System protection
overview, 11-2
System reset interrupt, 5-11
T
TA (transfer acknowledge) signal, 3-4, 13-6,
14-5, 14-33
TAP (test access port), see IEEE 1149.1 test
access port
TBREFU/TBREFL (timebase reference upper/lower)
registers, 11-25
TBSCR (timebase status and control) registers, 11-26
TBU/TBL (time base upper/lower) registers, 5-4
TBU/TBL (timebase upper/lower) registers, 11-24
TEA (tranfer error acknowledge) signal, 20-22
TEA (transfer error acknowledge)
signal, 3-4, 13-6, 14-5, 14-33
TESR (transfer error status register), 11-10
Test access port (TAP), see IEEE 1149.1 test access
port
Timebase, PowerPC, 11-24
Timer capture registers (TCR), 18-10, 18-11
Timer counter registers (TCN), 18-10
Timer event registers (TER), 18-11
Timer global configuration register
(TGCR), 18-8, 18-8
Timer mode register (TMR), 18-9
Index Index--15