Synchronous-Burst Memory Timing - Texas Instruments TMS320C6712D User Manual

timing requirements for synchronous-burst SRAM cycles
NO. NO.
6 t su(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high
7 t h(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high
† The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but
random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous-burst SRAM
†‡
cycles (see Figure 28 and Figure 29)
NO. NO.
1 t d(EKOH-CEV)
2 t d(EKOH-BEV)
3 t d(EKOH-BEIV)
4 t d(EKOH-EAV)
5 t d(EKOH-EAIV)
8 t d(EKOH-ADSV)
9 t d(EKOH-OEV)
10 t d(EKOH-EDV)
11 t d(EKOH-EDIV)
12 t d(EKOH-WEV)
† The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but
random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
‡ ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.

SYNCHRONOUS-BURST MEMORY TIMING

PARAMETER PARAMETER
Delay time, ECLKOUT high to CEx valid
Delay time, ECLKOUT high to BEx valid
Delay time, ECLKOUT high to BEx invalid
Delay time, ECLKOUT high to EAx valid
Delay time, ECLKOUT high to EAx invalid
Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid
Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid
Delay time, ECLKOUT high to EDx valid
Delay time, ECLKOUT high to EDx invalid
Delay time, ECLKOUT high to AWE/SDWE/SSWE valid
POST OFFICE BOX 1443
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
†
(see Figure 28)
•
HOUSTON, TEXAS 77251−1443
TMS320C6712D
−150
UNIT UNIT
MIN MAX
1.5 ns
2.5 ns
−150
UNIT UNIT
MIN MAX
1.2 7 ns
7 ns
1.2 ns
7 ns
1.2 ns
1.2 7 ns
1.2 7 ns
7 ns
1.2 ns
1.2 7 ns
73