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Texas Instruments AM243 Series Manuals
Manuals and User Guides for Texas Instruments AM243 Series. We have
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Texas Instruments AM243 Series manuals available for free PDF download: User Manual
Texas Instruments AM243 Series User Manual (62 pages)
GP EVM
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 8 MB
Table of Contents
Table of Contents
1
1 Introduction
3
EVM Revisions and Assembly Variants
4
2 Important Usage Notes
4
Power-On Usage Note
4
Table 1-1. Am64X/Am243X GP EVM PCB Design Revisions, and Asssembly Variants
4
6 Revision History
5
Figure 3-1. Top View of the Am64X/Am243X GP EVM Board
5
Key Features
6
Figure 3-2. Bottom View of the Am64X/Am243X GP EVM Board
6
Functional Block Diagram
8
Diagram
8
Power-On/Off Procedures
9
Power-On Procedure
9
Power-Off Procedure
10
Peripheral and Major Component Description
11
Am64X/Am243X Clock
11
Clocking
11
Ethernet PHY Clock
11
Figure 3-4. Am64X/Am243X GP EVM Clock Tree
11
Pcie Clock
11
Table 3-1. Source Clock Selection for the Clock Buffer
11
Figure 3-5. Overall Reset Architecture of the Am64X/Am243X GP EVM
12
Reset
12
Current Monitoring
13
Power
13
Power Input
13
Reverse Polarity Protection
13
Table 3-2. VMAIN LED
13
Table 3-3. INA Devices I2C Slave Address
13
Power Supply
14
Table 3-4. Power Test Points
14
Figure 3-6. Power Good Leds
15
Table 3-5. Power Leds
15
Figure 3-7. Power on and off Sequencing
16
Power Sequencing
16
Am64X/Am243X Power
17
Figure 3-8. Am64X/Am243X Core Supply and Array Core Supply Options
17
Boot Modes
18
Configuration
18
Table 3-6. Soc Power Supply
18
Figure 3-10. Am64X/Am243X GP EVP PCB, Boot Mode Selection Switches (SW2, SW3)
19
Figure 3-9. Am64X/Am243X GP EVM Schematic Excerpt, Boot Mode Selection Switches (SW2, SW3)
19
Table 3-7. BOOTMODE Bits
20
Table 3-8. PLL Reference Clock Selection BOOTMODE[2:0]
20
Table 3-9. Boot Device Selection BOOTMODE[6:3]
20
Table 3-10. Primary Boot Media Configuration BOOTMODE[9:7]
21
Table 3-11. Backup Boot Mode Selection BOOTMODE[12:10]
21
Table 3-12. Backup Boot Media Configuration BOOTMODE[13]
21
Jtag
22
Table 3-13. Selection of HSE Connector and JTAG TRACE Functionality
22
Table 3-14. TI20 Pin Connector (J25) Pin-Out
22
Figure 3-11. JTAG Interface
23
Table 3-15. TI 60-Pin Connector (J33) Pin-Out
24
Table 3-16. List of Signals Routed to Test Automation Header
25
Test Automation
25
Figure 3-12. Test Automation Header
26
Table 3-17. Test Automation Header (J38) Pin-Out
27
Figure 3-13. Am64X/Am243Xuart Interfaces
28
UART Interfaces
28
DDR4 Interface
29
Figure 3-14. Am64X/Am243X DDR4 Interface
29
Memory Interfaces
29
Figure 3-15. Micro SD Interface
30
MMC Interfaces
30
Figure 3-16. Emmc Interface
31
OSPI Interface
31
Board ID EEPROM Interface
32
Figure 3-17. Am64X/Am243X OSPI Interface
32
SPI EEPROM Interface
32
Table 3-18. Board ID Memory Header Information
32
Ethernet Interface
33
Figure 3-18. Ethernet Interface - CPSW Domain
33
Figure 3-19. Ethernet Interface - ICSSG Domain
34
DP83867 PHY Default Configuration
35
DP83869 PHY Default Configuration
35
Table 3-19. Default Strap Setting of CPSW Ethernet PHY
36
Table 3-20. Default Strap Setting of ICSSG Ethernet Phys
36
Figure 3-20. Am64X/Am243Xethernet Interfaces - CPSW Ethernet Strap Settings
39
Figure 3-21. Am64X/Am243X Ethernet Interfaces - ICSSG1 Ethernet Strap Settings
40
Figure 3-22. Am64X/Am243X Ethernet Interfaces - ICSSG2 Ethernet Strap Settings
41
Ethernet LED
42
Figure 3-23. Am64X/Am243X GP EVM Ethernet Interface LED
42
Display Interface
43
Table 3-21. Display Connector (J36) Pin-Out
43
Figure 3-24. Am64X/Am243X USB 2.0 Host Interface
44
Pcie Interface
44
USB 2.0 Interface
44
Figure 3-25. Am64X/Am243X Pcie Interface
45
Table 3-22. Pcie Jumper Options to Enable Root Complex and Endpoint Mode
45
Table 3-23. Pcie Connector (J27) Pin-Out
45
High Speed Expansion Interface
46
Table 3-24. Selection of PRG0 Signals on Application Connector
47
Figure 3-26. Am64X/Am243X High Speed Expansion Connector
52
Figure 3-27. Am64X/Am243X High Speed Expansion Connector - Part 1
53
CAN Interface
54
Figure 3-28. Am64X/Am243X High Speed Expansion Connector - Part 2
54
Table 3-25. CAN (J31 and J32) Pin-Out
54
ADC Interface
55
Figure 3-29. Am64X/Am243X CAN Interfaces
55
Interrupt
55
Table 3-26. ADC Connector (J3) Pin-Out
55
I2C Interfaces
56
Safety Connector
56
SPI Interfaces
56
Table 3-27. Safety Connector Pinouts
56
Table 3-28. I2C Test Header (J5) Pin-Out
56
Figure 3-30. Am64X/Am243X I2C Interfaces and Address Assignment of Peripherals
57
Table 3-29. I2C Test Header (J4) Pin-Out
57
Figure 3-31. Am64X/Am243X FSI Interface
58
FSI Interface
58
Table 3-30. FSI (J5) Connector Pin-Out
58
4 Known Issues and Modifications
59
Issue 1 - Embedded XDS110 Connection to Am64X Target in CCS
59
Figure 4-1. Am64X/Am243X GP EVM Modification Label Location
59
Table 4-1. Am64X/Am243X GP EVM Known Issues and Modifications
59
Figure 4-2. XDS110 CCS Connection Error Dialog
60
Figure 4-3. XDS110 Debug Reset Utility Command-Line Function
60
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Texas Instruments AM243 Series User Manual (53 pages)
Brand:
Texas Instruments
| Category:
Microcontrollers
| Size: 4 MB
Table of Contents
Table of Contents
1
Preface: Read this First
3
If You Need Assistance
3
Important Usage Notes
3
Kit Overview
4
Figure 2-1. Am243X Launchpad Board
4
Kit Contents
5
Key Features
5
Figure 2-2. System Architecture
5
Component Identification
6
Figure 2-3. Am243X Launchpad Top Component Identification
6
Figure 2-4. Am243X Launchpad Bottom Component
6
Boosterpacks
7
Compliance
7
Board Setup
7
Power Requirements
7
Power Input Using USB Type-C Connector
7
Figure 3-1. Type-C CC Configuration
8
Figure 3-2. USB Type-C Power Input
8
Table 3-1. Current Sourcing Capability and State of USB Type-C Cable
8
Power Status Led's
9
Figure 3-3. Power Status Led's
9
Table 3-2. Power Status Led's
9
Power Tree
10
Figure 3-4. Power Tree Diagram of Am243X Launchpad
10
Power Sequence
11
Push Buttons
11
Figure 3-5. Power Sequence
11
Table 3-3. Launchpad Push Buttons
11
Boot Mode Selection
12
Universal Asynchronous Receiver/Transmitter (UART)
12
Table 3-4. Boot-Mode Selection Table
12
Figure 3-6. Boot-Mode DIP Switch
12
Hardware Description
13
Functional Block Diagram
13
Figure 4-1. Am243X Launchpad Functional Block Diagram
13
Boosterpack Headers
14
Figure 4-2. Boosterpack Header Pinout
14
Figure 4-3. Site #2 Boosterpack Header
15
Table 4-1. Boosterpack Power Sourcing for Boosterpack Site #2
15
Pinmux for Boosterpack
16
Figure 4-4. 80 Pin Boosterpack Pinout
16
Table 4-2. Pinmux Options for J1/J3 Connector - Site 1
17
Table 4-3. Net Name in Schematic and Package Signal Name for J1/J3 Connector
18
Table 4-4. Pinmux Options for J2/J4 Connector - Site 1
19
Table 4-5. Net Name in Schematic and Package Signal Name for J2/J4 Connector
20
Table 4-6. Pinmux Options for J5/J7 Connector - Site 2
21
Table 4-7. Net Name in Schematic and Package Signal Name for J5/J7 Connector
22
Table 4-8. Pinmux Options for J6/J8 Connector - Site 2
23
Table 4-9. Net Name in Schematic and Package Signal Name for J6/J8 Connector
24
GPIO Mapping
25
Table 4-10. GPIO Mapping Table
25
Reset
27
Figure 4-5. Reset Architecture
27
Clock
28
Figure 4-6. Clock Architecture
28
Table 4-11. Clock Frequency Table
28
Memory Interface
29
QSPI Interface
29
Figure 4-7. QSPI Interface
29
Board ID EEPROM
30
Figure 4-8. Board ID EEPROM
30
Table 4-12. Board ID Memory Header Information
30
Ethernet Interface
31
Figure 4-9. Ethernet Connection
31
Ethernet PHY Strapping
32
Figure 4-10. CPSW or PRG RGMII1 Ethernet Data Mux
32
Figure 4-11. Ethernet PHY Strapping for RGMII1 PHY
33
Figure 4-12. Ethernet PHY Strapping for RGMII2 PHY
33
Ethernet PHY - Power, Clock, Reset, Interrupt
34
LED Indication in Ethernet RJ45 Connector
34
Table 4-13. Ethernet PHY Strapping Values
34
USB 2.0 Interface
35
I2C Interface
35
Figure 4-13. USB 2.0 Interface
35
Figure 4-14. I2C Interface
35
Industrial Application Leds
36
Figure 4-15. Industrial Application Leds
36
UART Interface
37
Figure 4-16. UART Interface
37
Eqep Interface
38
Figure 4-17. Eqep Interface
38
Figure 4-18. Eqep1 Header
38
Figure 4-19. Eqep2 Header
39
Figure 4-20. Eqep2 or MCAN0 Mux Selection Circuit
39
CAN Interface
40
Figure 4-21. CAN Interface
40
Figure 4-22. MCAN Transceiver and Header
40
FSI Interface
41
Figure 4-23. FSI Interface
41
Table 4-14. FSI Header Pin Description
41
Figure 4-24. FSI Header
42
Figure 4-25. FSI or Boosterpack Mux Selection Circuit
42
JTAG Emulation
43
Figure 4-26. JTAG Interface
43
Figure 4-27. Micro-B USB Connection for JTAG
43
Test Automation Interface
44
Figure 4-28. Test Automation Header
44
Table 4-15. Test Automation Signal Description
44
Table 4-16. Test Automation Header Pinout
45
SPI Interface
46
Figure 4-29. SPI Connection from Soc to Boosterpack Connector
46
Reference Documents
47
Other TI Components Used in this Design
47
Revision History
47
Texas Instruments AM243 Series User Manual (83 pages)
Brand:
Texas Instruments
| Category:
Microcontrollers
| Size: 3 MB
Table of Contents
Table of Contents
1
Kit Overview
4
Kit Contents
5
Key Features
5
Component Identification
6
Boosterpacks
7
Compliance
7
Board Setup
7
Power Requirements
7
Power Input Using USB Type-C Connector
7
Power Status Led's
9
Figure 3-3. Power Status Led's
9
Table 3-2. Power Status Led's
9
Power Tree
10
Power Sequence
11
Push Buttons
11
Figure 3-5. Power Sequence
11
Table 3-3. Launchpad Push Buttons
11
Boot Mode Selection
12
Figure 3-6. Boot-Mode DIP Switch
12
Table 3-4. Boot-Mode Selection Table
12
Hardware Description
13
Functional Block Diagram
13
Boosterpack Headers
14
Table 4-3. Net Name in Schematic and Package Signal Name for J1/J3 Connector
18
Table 4-5. Net Name in Schematic and Package Signal Name for J2/J4 Connector
20
Table 4-7. Net Name in Schematic and Package Signal Name for J5/J7 Connector
22
Table 4-9. Net Name in Schematic and Package Signal Name for J6/J8 Connector
24
Table 4-10. GPIO Mapping Table
25
Figure 4-6. Clock Architecture
28
Table 4-11. Clock Frequency Table
28
Figure 4-23. FSI Interface
41
Figure 4-24. FSI Header
41
Figure 4-28. Test Automation Header
45
Figure 4-8. Board ID EEPROM
63
Table 4-12. Board ID Memory Header Information
63
Figure 4-9. Ethernet Connection
64
Figure 4-10. CPSW or PRG RGMII1 Ethernet Data Mux
65
Figure 4-11. Ethernet PHY Strapping for RGMII1 PHY
66
Figure 4-12. Ethernet PHY Strapping for RGMII2 PHY
66
Table 4-13. Ethernet PHY Strapping Values
67
Figure 4-13. USB 2.0 Interface
68
Figure 4-14. I2C Interface
68
Figure 4-15. Industrial Application Leds
69
Figure 4-16. UART Interface
70
Figure 4-17. Eqep Interface
71
Figure 4-18. Eqep1 Header
71
Figure 4-19. Eqep2 Header
72
Figure 4-20. Eqep2 or MCAN0 Mux Selection Circuit
72
Figure 4-21. CAN Interface
73
Figure 4-22. MCAN Transceiver and Header
73
Table 4-14. FSI Header Pin Description
74
Table 4-16. Test Automation Header Pinout
78
Table A-1. E3 RJ45 Connector
81
Table A-2. E3 GPIO Mapping
81
Table A-3. E3 Ethernet PHY Signal Mapping
82
Table A-4. E3 LED ACT Signal Resistor Mounting
82
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