Figure 18.66 Tciv Interrupt Setting Timing; Figure 18.67 Tciu Interrupt Setting Timing - Renesas HD6417641 Hardware Manual

32-bit risc microcomputer superh risc engine family / sh7641 series
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TCFV Flag/TCFU Flag Setting Timing: Figure 18.66 shows the timing for setting of the TCFV
flag in TSR on overflow, and TCIV interrupt request signal timing.
Figure 18.67 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU
interrupt request signal timing.
TCNT input
clock
TCNT
(overflow)
Overflow
signal
TCFV flag
TCIV interrupt
TCNT
input clock
TCNT
(underflow)
Underflow
signal
TCFU flag
TCIU interrupt
H'FFFF

Figure 18.66 TCIV Interrupt Setting Timing

H'0000

Figure 18.67 TCIU Interrupt Setting Timing

Section 18 Multi-Function Timer Pulse Unit (MTU)
H'0000
H'FFFF
Rev. 4.00 Sep. 14, 2005 Page 625 of 982
REJ09B0023-0400

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