Figure 9.41 Tciv Interrupt Setting Timing; Figure 9.42 Tciu Interrupt Setting Timing - Renesas H8SX/1500 Series Hardware Manual

32-bit cisc microcomputer
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(3)
TCFV Flag/TCFU Flag Setting Timing
Figure 9.41 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the
TCIV interrupt request signal timing.
Figure 9.42 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and
the TCIU interrupt request signal timing.
TCNT input
clock
TCNT
(overflow)
Overflow signal
TCFV flag
TCIV interrupt
TCNT input
clock
TCNT
(underflow)
Underflow signal
TCFU flag
TCIU interrupt
H'FFFF

Figure 9.41 TCIV Interrupt Setting Timing

H'0000

Figure 9.42 TCIU Interrupt Setting Timing

Section 9 16-Bit Timer Pulse Unit (TPU)
H'0000
H'FFFF
Rev. 3.00 Mar. 14, 2006 Page 335 of 804
REJ09B0104-0300

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