Single Transfer Mode - Renesas M16C/64C User Manual

M16C/64C Group
16.3.5

Single Transfer Mode

In single transfer mode, the transfer stops when the DMAi transfer counter underflows. Figure 16.3
shows an Operation Example in Single Transfer Mode.
Single Transfer Mode
Bus CPU
DMAS bit
TCRi register
Undefined
IR bit
DMAE bit
i = 0 to 3
DMAS, DMAE: Bits in the DMiCON register
IR: Bit in the DMiIC register
The above assumes the following:
The TCRi register value is 02h (there are three transfers).
Figure 16.3 Operation Example in Single Transfer Mode
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
DMA CPU
When a DMA transfer begins, the DMAS bit becomes 0.
02h 01h
Reload
Set to 1 by a program.
DMA CPU DMA
Underflow
00h
Set to 0 by an interrupt request acknowledgement
CPU
FFh
or by a program.
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16. DMAC