Transfer Cycle - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

1. Transfer Cycle

The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination
write) bus cycle. The number of read and write bus cycles is affected by the source and destination
addresses of transfer. During memory expansion and microprocessor modes, it is also affected by the
BYTE pin level. Furthermore, the bus cycle itself is extended by a software wait or RDY signal.
(a) Effect of Source and Destination Addresses
If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd
address, the source read cycle consists of one more bus cycle than when the source address of
transfer begins with an even address.
Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer
begins with an odd address, the destination write cycle consists of one more bus cycle than when the
destination address of transfer begins with an even address.
(b) Effect of BYTE Pin Level
During memory expansion and microprocessor modes, if 16 bits of data are to be transferred on an 8-
bit data bus (input on the BYTE pin = high), the operation is accomplished by transferring 8 bits of data
twice. Therefore, this operation requires two bus cycles to read data and two bus cycles to write data.
Furthermore, if the DMAC is to access the internal area (internal ROM, internal RAM, or SFR), unlike
in the case of the CPU, the DMAC does it through the data bus width selected by the BYTE pin.
(c) Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of
bus cycles required for that access increases by an amount equal to software wait states.
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(d) Effect of RDY Signal
During memory expansion and microprocessor modes, DMA transfers to and from an external area
are affected by the RDY signal. Refer to "RDY Signal".
Figure 1.12.5 shows the example of the cycles for a source read. For convenience, the destination write
cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality,
the destination write cycle is subject to the same conditions as the source read cycle, with the transfer
cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for
the source read and the destination write cycle, respectively. For example, when data is transferred in 16-
bit unit using an 8-bit bus ((2) in Figure 1.12.5), two source read bus cycles and two destination write bus
cycles are required.
Rev.1.00 2003.05.30 page 92
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DMAC
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